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ST7MC1/ST7MC2
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
PRODUCT PREVIEW
s
s
s
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Memories - 8K to 60K dual voltage FLASH Program memory or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming. - 384 to 1.5K RAM - HDFlash endurance: 100 cycles, data retention: 20 years Clock, Reset And Supply Management - Enhanced reset system - Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability - Clock sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system. - Four power saving modes: Halt, Active-Halt, Wait and Slow Interrupt Management - Nested interrupt controller - 14 interrupt vectors plus TRAP and RESET - MCES top level interrupt pin - 16 external interrupt lines (on 3 vectors) Up to 60 I/O Ports - up to 60 multifunctional bidirectional I/O lines - up to 41 alternate function lines - up to 11 high sink outputs 5 Timers - Main Clock Controller with: Real time base, Beep and Clock-out capabilities - Configurable window watchdog timer - Two 16-bit timers with: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes - 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
TQFP80 14 x 14
TQFP64 14 x 14
TQFP44 10 x 10
TQFP32 7x7
s
SDIP56
SDIP32
s
s s s
s
2 Communication Interfaces - SPI synchronous serial interface - LINSCI asynchronous serial interface Brushless Motor Control Peripheral - 6 high sink PWM output channels for sinewave or trapezoidal inverter control - Motor safety including asynchronous emergency stop and write-once registers - 4 analog inputs for rotor position detection (sensorless/hall/tacho/encoder) - Permanent magnet motor coprocessor including multiplier, programmable filters, blanking windows and event counters - Operational amplifier and comparator for current/voltage mode regulation and limitation Analog peripheral - 10-bit ADC with 16 input pins In-circuit Debug Instruction Set - 8-bit Data Manipulation - 63 Basic Instructions - 17 main Addressing Modes - 8 x 8 Unsigned Multiply Instruction - True Bit Manipulation Development Tools - Full hardware/software development package
ST7MC2
Device Summary
Features
Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply vs. Frequency Temperature Range Package -40C to +85C / -40C to +125C SDIP32/TQFP32 TQFP44
ST7MC1
8K 384 (256)
16K 24K 32K 48K 768 (256) 1024 (256) 1024 (256) 1536 (256) Watchdog, 16-bit Timer A, LINSCI, 10-bit ADC, MTC, 8-bit PWM ART, ICD SPI, 16-bit Timer B 4.5 to 5.5V with fCPU8MHz -40C to +85 C SDIP56/TQFP64 TQFP64
60K 1536 (256)
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TQFP80
Rev. 2.1
April 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
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1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 4.3 4.4 4.5 4.6 4.7 4.8 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 5.3 5.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 32
6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 6.3 6.4 6.5 6.6 6.7 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 43
7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 7.3 7.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 8.3 8.4 8.5 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 9.3 9.4 9.5 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 294 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . 103
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9.6 9.7 9.8 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 11.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 11.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 11.3 6OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 11.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 11.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 11.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 11.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 11.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 266 11.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 11.13 OPERATIONAL AMPLIFIER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 12 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 12.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 13 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 284 13.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 286 13.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
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ST7MC1/ST7MC2
1 INTRODUCTION
The ST7MCx device is member of the ST7 microcontroller family designed for mid-range applications with a Motor Control dedicated peripheral. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH, ROM or FASTROM program memory. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Figure 1. Device Block Diagram
8-BIT CORE ALU RESET VPP VSS VDD CONTROL PROGRAM MEMORY (8K - 60K Bytes) RAM (384 - 1536Bytes) PORT H 1) PH7:0 1) (8-bits) PG7:0 1) (8-bits)
LVD AVD
OSC1 OSC2
OSC ADDRESS AND DATA BUS SCI/LIN
PORT G 1)
WATCHDOG PWM ART PORT A
PORT D PD7:0 (8-bits) TIMER A 10-BIT ADC VAREF VSSA PORT E1 PE5:0 (6-bits) TIMER B 1
PA7:0 1) (8-bits)
PORT B MTC VOLT INPUT SPI 1 PB7:0 (8-bits)
PORT C PORT F1 PF5:0 (6-bits) MCC/RTC/BEEP1 PC7:0 (8-bits) MOTOR CONTROL MCES DEBUG MODULE
On some devices only, see Table 1, "ST7MC Device Pin Description," on page 11
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ST7MC1/ST7MC2
2 PIN DESCRIPTION
Figure 2. 80-Pin TQFP 14x14 Package Pinout
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
MCO2 (HS) MCO1 (HS) MCO0 (HS) VPP/ICCSEL PE5 PE4 / EXTCLK_B PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0 (HS) / OCMP2_B PH7 PH6 PH5 PH4 VDD_2 VSS_2 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 /EXTCLK_A / AIN14 / ICCCLK
(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES PG0 PG1 PG2 PG3 OSC1 OSC2 VSS_1 VDD_1 PWM3 / PA0 PWM2 / (HS) PA1 PWM1 / PA2 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 ARTIC2 / PA6 AIN2 / PA7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ei0
ei1
ei1
ei2
ei2
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / AIN12 PD1 (HS) / OCMP1_A PD0 / OCMP2_A / AIN11 PH3 PH2 PH1 PH0 PF5 (HS) PF4 (HS)
PF3 (HS) / BEEP
PF2 / MCO / AIN10 PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 RESET
VDD_0
VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7
MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 /SS /(HS) PB7 PG4 PG5 PG6 PG7
(HS) PC0 AIN5 / MCCFI 0/ PC1 OAP / PC2 OAN / PC3 AIN6 / MCCFI 1/ OAZ * MCCREF / PC4
(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
MCPWMU/ PC5 MCPWMV/ PC6
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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ST7MC1/ST7MC2
Figure 3. 64-Pin TQFP 14x14 Package Pinout
MCO2 (HS) MCO1 (HS) MCO0 (HS) VPP /ICCSEL PE5 / PE4 / EXTCLK_B PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0 (HS) / OCMP2_B VDD_2 VSS_2 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 /EXTCLK_A / AIN14 / ICCCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 ei0 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 ei1 36 13 35 14 ei2 34 15 ei1 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS /(HS) PB7 (HS) PC0 AIN5 / MCCFI0 / PC1 OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ * MCCREF / PC4 MCPWMU / PC5 MCPWMV/ PC6
(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 VSS_1 VDD_1 PWM3 / PA0 PWM2 / (HS) PA1 PWM1 / PA2 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 ARTIC2 / PA6 AIN2 / PA7
PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / AIN12 PD1 (HS) / OCMP1_A PD0 / OCMP2_A / AIN11 PF5 (HS) PF4 (HS) PF3 (HS) / BEEP PF2 / MCO / AIN10 PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 RESET VDD_0 VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7
(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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ST7MC1/ST7MC2
Figure 4. 32-Pin SDIP Package Pinouts
ICCSEL / VPP MCO0 MCO1 MCO2 MCO3 MCO4 MCO5 MCES OSC1 OSC2 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 / EXTCLK_A / AIN14 / ICCCLK PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / MCZEM / AIN12 PD1 (HS) / OCMP1_A / MCPWMV / MCDEM PD0 / OCMP2_A / MCPWMW / AIN11 RESET VDD_0 VSS_0 VAREF PC4 / MCCREF * OAZ / MCCFI1 / AIN6 PC3 / OAN PC2 / OAP
ei0
28 27 26 25 24 23 22
ei1
21 20 19 18
ei2
17
(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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ST7MC1/ST7MC2
Figure 5. 56-Pin SDIP Package Pinouts
OCMP1_B / PE1 ICAP2_B / PE2 ICAP1_B / PE3 VPP/ICCSEL (HS) MCO0 (HS) MCO1 (HS) MCO2 (HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 Vss_1 Vdd_1 PWM2 / (HS) PA1 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 ARTIC2 / PA6 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS /(HS) PB7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ei2 ei2 ei1 ei0
56 55 54 53 52 51 50 49 48 47
46
PE0 (HS) / OCMP2_B VDD_2 VSS_2 PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA PD4 /EXTCLK_A / AIN14 / ICCCLK PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / AIN12 PD1 (HS) / OCMP1_A PD0 / OCMP2_A / AIN11 PF3 (HS) / BEEP PF1 / MCZEM / AIN9 PF0 / MCDEM / AIN8 RESET VDD_0 VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7 PC6 / MCPWMV PC5 / MCPWMU PC4 / MCCREF * OAZ / MCCFI1 / AIN6 PC3 / OAN PC2 / OAP PC1 / MCCFI0/AIN5 PC0(HS)
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
ei1
(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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ST7MC1/ST7MC2
Figure 6. 44-Pin TQFP Package Pinouts
PE3 / ICAP1_B PE2 / ICAP2_B PE1 / OCMP1_B PE0 (HS) / OCMP2_B PD7 (HS) / TDO PD6 (HS) / RDI PD5 / AIN15 / ICCDATA
(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 VSS_1 VDD_1 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 MCVREF / PB0
44 43 42 41 40 39 38 37 36 35 34 1 33 2 ei0 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 ei1 10 24 ei2 11 23 12 13 14 15 16 17 18 19 20 21 22 MCIA / PB1 MCIB / PB2 MCIC / PB3 MISO / PB4 AIN3 / MOSI / PB5 SCK / (HS) PB6 AIN4 / SS /(HS) PB7 OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ * MCCREF / PC4
VPP /ICCSEL
MCO2 (HS)
MCO1 (HS) MCO0 (HS)
PD4 /EXTCLK_A / AIN14 / ICCCLK PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / MCZEM / AIN12 PD1 (HS) / OCMP1_A / MCPWMV/MCDEM PD0 / OCMP2_A / AIN11 RESET VDD_0 VSS_0 VSSA VAREF PC7 / MCPWMW / AIN7
(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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ST7MC1/ST7MC2
Figure 7. 32-Pin TQFP 7x7 Package Pinout
PD4 /EXTCLK_A / AIN14 / ICCCLK
(HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5
32 31 30 29 28 27 26 25 24 1 23 2 ei0 22 3 21 4 20 5 19 6 18 7 ei2 ei1 17 8 9 10 11 12 13 14 15 16 MCVREF / PB0 MCIA / PB1 MCIB / PB2 MCIC / PB3 OAP / PC2 OAN / PC3 AIN6 / MCCFI1 / OAZ * MCCREF / PC4
PD5 / AIN15 / ICCDATA
PD7 (HS) / TDO PD6 (HS) / RDI
VPP /ICCSEL
MCO2 (HS) MCO1 (HS) MCO0 (HS)
PD3 / ICAP1_A / AIN13 PD2 / ICAP2_A / MCZEM / AIN12 PD1 (HS) / OCMP1_A / MCPWMV / MCDEM PD0 / OCMP2_A / MCPWMW /AIN11 RESET VDD_0 VSS_0 VAREF
(HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O
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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, See "ELECTRICAL CHARACTERISTICS" on page 243. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger TT= Refer to the G&H ports Characteristics in section 11.8.1 on page 260 Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt 1), ana = analog - Output: OD = open drain, PP = push-pull Refer to "I/O PORTS" on page 50 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 1. ST7MC Device Pin Description
Pin n TQFP80 TQFP64 TQFP44 TQFP32 Type SDIP56 SDIP32 Pin Name Level Output Input Port Input float wpu ana int Main Outp function ut (after reset) OD PP Alternate function 2)
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2 3 4 5 6 7 8 9
8 9 10 11 12 13 14 15 -
1 2 3 4 5 6 7 8 9 -
5 6 7 8 9 10 11 -
1 2 3 4 5 6 7 8 -
MCO3 (HS) MCO4 (HS) MCO5 (HS) MCES3) PG0 PG1 PG2 PG3 OSC14) OSC24) Vss_1 Vdd_1 PA0/PWM3 PA1/PWM2 PA2PWM1 PA3/PWM0/ AIN0
O O O I CT I/O TT I/O TT I/O TT I/O TT I I/O S S I/O CT I/O CT I/O CT I/O CT
HS HS HS input wpd + int XX XX XX XX
X Motor Control Output 3 X Motor Control Output 4 X Motor Control Output 5 MTC Emergency Stop X X Port G0 X X Port G1 X X Port G2 X X Port G3 External clock input or Resonator oscillator inverter input Resonator oscillator inverter output Digital Ground Voltage Digital Main Supply Voltage XX X X Port A0 X X Port A1 X X Port A2 ei1 X X X Port A3 X X Port A4 ei1 X X X Port A5 ei1 X X Port A6 PWM Output 3 PWM Output 2 PWM Output 1 PWM Output 0 ADC Analog Input 0
14 10 16 15 11
HS
XX XX X
16 12 17 17 13 18
PA4 (HS)/ARTI/O CT CLK PA5 / ARTIC1/ I/O CT AIN1 PA6 / ARTIC2 PA7/AIN2 I/O CT I/O CT
HS
XX X X X
PWM-ART External Clock PWM-ART Input Capture 1 ADC Analog Input 1
18 14 19 10 12 19 15 20 20 16 -
PWM-ART Input Capture 2 ADC Analog Input 2
ei1 X X X Port A7
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Pin n TQFP80 TQFP64 TQFP44 TQFP32 Type SDIP56 SDIP32 Pin Name Level Output Input Port Input float wpu ana int Main Outp function ut (after reset) OD PP Alternate function 2)
21 17 21 11 13
9
PB0/MCVREF I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I/O TT I/O TT I/O CT HS HS HS
XX XX XX XX XX XX X X XX XX XX XX X X ei2 ei2 ei2 ei2
X X X Port B0 X X X Port B1 X X X Port B2 X X X Port B3 X X Port B4 X X Port B5 X X Port B6 X X Port B7 X X Port G4 X X Port G5 X X Port G6 X X Port G7 X X Port C0 X X X Port C1
MTC Voltage Reference MTC Input A MTC Input B MTC Input C SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Slave Select (active low) ADC Analog Input 3
22 18 22 12 14 10 PB1/MCIA 23 19 23 13 15 11 PB2/MCIB 24 20 24 14 16 12 PB3/MCIC 25 21 25 15 26 22 26 16 27 23 27 17 28 24 28 18 29 30 31 32 PB4/MISO PB5/MOSI/ AIN3 PB6/SCK PB7/SS/AIN4 PG4 PG5 PG6 PG7 PC0
SPI Serial Clock ADC Analog Input 4
33 25 29 34 26 30
PC1/MCCFI05) I/O CT /AIN5 I/O CT I/O CT I/O
MTC Current Feedback Input 05)
ADC Analog Input 5
35 27 31 19 17 13 PC2/OAP 36 28 32 20 18 14 PC3/OAN OAZ/ 37 29 33 21 19 15 MCCFI15)/ AIN6
X X
ei2 X X X Port C2 ei2 X X X Port C3 X Opamp Output
OPAMP Positive Input OPAMP Negative Input MTC Current Feedback Input 15) ADC analog Input 6
38 30 34 22 20 16 PC4/MCCREF I/O CT 39 31 35 40 32 36 PC5/MCPWMU PC6/ MCPWMV7) PC7/ MCPWMW7)/ AIN7 I/O CT I/O CT I/O CT I S S S I/O CT
XX XX XX XX
X X X Port C4 X X Port C5 X X Port C6 X X X Port C7
MTC Current Feedback Reference 9) MTC PWM Output U MTC PWM Output V7) MTC PWM Output W7) ADC Analog Input 7
41 33 37 23
42 34 38 24 21 17 VAREF 43 35 39 25 - VSSA 44 36 40 26 22 18 VSS_0 45 37 41 27 23 19 VDD_0 46 38 42 28 24 20 RESET
Analog Reference Voltage for ADC Analog Ground Voltage Digital Ground Voltage Digital Main Supply Voltage Top priority non maskable interrupt
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Pin n TQFP80 TQFP64 TQFP44 TQFP32 Type SDIP56 SDIP32 Pin Name Level Output Input Port Input float wpu ana int Main Outp function ut (after reset) OD PP Alternate function 2)
47 39 43 48 40 44 49 41 -
-
-
-
PF0/ MCDEM6)/ AIN8
I/O CT
XX XX XX HS HS HS XX XX XX XX XX XX XX X
X X X Port F0 X X X Port F1 X X X Port F2 X X Port F3 X X Port F4 X X Port F5 X X Port H0 X X Port H1 X X Port H2 X X Port H3
MTC DeADC Anamagnetiza6) log Input 8 tion Output MTC BEMF Output6) Main Clock Out (fosc/2) ADC Analog Input 9 ADC Analog Input 10
PF1/MCZEM6)/ I/O CT AIN9 PF2/MCO/ AIN10 PF3/BEEP PF4 PF5 PH0 PH1 PH2 PH3 I/O CT I/O CT I/O CT I/O CT I/O TT I/O TT I/O TT I/O TT I/O CT
50 42 45 51 43 52 44 53 54 55 56 -
Beep Signal Output
PD0/ OCMP2_A/ 57 45 46 29 25 21 MCPWMW7)/ AIN11 PD1 (HS)/ OCMP1_A/ 58 46 47 30 26 22 MCPWMV7)/ MCDEM6)
Timer A Output Compare 2 X X X Port D0 MTC PWM Output W7) ADC Analog Input 11 Timer A Output Compare 1 I/O CT HS X ei0 X X Port D1 MTC PWM Output V7) MTC Demagnetization6) Timer A Input Capture 2 X ei0 X X X Port D2 MTC BEMF6) ADC Analog Input 12 X ei0 X X X Port D3 Timer A Input Capture 1 ADC Analog Input 13
PD2/ICAP2_A/ 59 47 48 31 27 23 MCZEM5) / I/O CT AIN12 60 48 49 32 28 24 PD3/ICAP1_A/ I/O CT AIN13
PD4/ 61 49 50 33 29 25 EXTCLK_A/IC- I/O CT CCLK/AIN14 62 50 51 34 30 26 PD5/ICCDATA/AIN15 I/O CT I/O CT I/O CT S S I/O TT I/O TT I/O TT I/O TT HS HS
Timer A External Clock source X ei0 X X X Port D4 ICC Clock Output ADC Analog Input 14 X X XX ei0 ei0 X X X Port D5 X X Port D6 X X Port D7 ICC Data Input ADC Analog Input 15 SCI Receive Data In SCI Transmit Data Output
63 51 52 35 31 27 PD6/RDI 64 52 53 36 32 28 PD7/TDO 65 53 54 66 54 55 67 68 69 70 VSS_2 VDD_2 PH4 PH5 PH6 PH7
Digital Ground Voltage Digital Main Supply Voltage XX XX XX XX X X Port H0 X X Port H1 X X Port H2 X X Port H3 0
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Pin n TQFP80 TQFP64 TQFP44 TQFP32 Type SDIP56 SDIP32 Pin Name Level Output Input Port Input float wpu ana int Main Outp function ut (after reset) OD PP Alternate function 2)
71 55 56 37 72 56 73 57 74 58 75 59 76 60 1 2 3 38 39 40 -
-
-
PE0/ OCMP2_B PE1/ OCMP1_B PE2/ICAP2_B
I/O CT I/O CT I/O CT
HS
XX XX XX XX XX XX
X X Port E0 X X X Port E1 X X Port E2 X X X Port E3 X X Port E4 X X X Port E5
Timer B Output Compare 2 Timer B Output Compare 1 Timer B Input Capture 2 Timer B Input Capture 1 Timer B External Clock source
PE3/ICAP1_B/ I/O CT PE4/ I/O CT EXTCLK_B PE5 I/O CT
77 61
4
41
1
29 VPP/ICCSEL
I
Must be tied low. In the programming mode when available, this pin acts as the programming voltage input VPP./ ICC mode pin. See section 11.9.2 on page 264 HS HS HS X MTC Output Channel 0 X MTC Output Channel 1 X MTC Output Channel 2
78 62 79 63 80 64
5 6 7
42 43 44
2 3 4
30 MCO0 (HS) 31 MCO1 (HS) 32 MCO2 (HS)
O O O
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMV and MCDEM on PD1 on TQFP32), the two signals will be ORed on the output pin. 4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see Section 1 INTRODUCTION and Section 11.5 CLOCK AND TIMING CHARACTERISTICS for more details. 5. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows: - either to use PC1 as a standard I/O and map MCCFI on AOZ with or without using the operational amplifier (selected case after reset), - or to map MCCFI on PC1 and use the amplifier for another function. The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for more details. 6. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins. MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages. 7. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages. MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package. 8. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O.
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3 REGISTER & MEMORY MAP
As shown in Figure 8, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. Figure 8. Memory Map
0000h 007Fh 0080h
The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reseved area can have unpredictable effects on the device.
HW Registers (see Table 2)
0080h
Short Addressing RAM (zero page)
00FFh 0100h
RAM (1536/1024 768/384 Bytes)
067Fh 0680h
256 Bytes Stack
01FFh 0200h
1000h
60 KBytes
Reserved
0FFFh 1000h
16-bit Addressing RAM
01FFh or 037Fh or 047Fh or 067Fh
4000h
48 KBytes
8000h A000h E000h
32 KBytes 24 KBytes
Program Memory (60K, 48K, 32K, 24K, 8K)
FFDFh FFE0h FFFFh
Interrupt & Reset Vectors (see Table 8)
8 KBytes
FFFFh
As shown in Figure 9, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 1536 bytes of RAM and up to 60 Kbytes of user program memo-
ry. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h SPIDR SPICR SPICSR ITSPR0 ITSPR1 ITSPR2 ITSPR3 EICR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR PGDR PGDDR PGOR PHDR PHDDR PHOR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCICR3 SCIERPR SCIETPR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Port B Option Register Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Port F Option Register Port G Data Register Port G Data Direction Register Port G Option Register Port H Data Register Port H Data Direction Register Port H Option Register SCI SCI SCI SCI SCI SCI SCI SCI Status Register Data Register Baud Rate Register Control Register 1 Control Register 2 Control Register 3 Extended Receive Prescaler Register Extended Transmit Prescaler Register Reserved Area (1 Byte) SPI Data I/O Register SPI Control Register SPI Control/Status Register Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register xxh 0xh 00h FFh FFh FFh FFh 00h R/W R/W R/W R/W R/W R/W R/W R/W Reset Status 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h 00h1) 00h 00h C0h xxh 00h xxh 00h 00h 00h 00h Remarks R/W R/W R/W2) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W2) R/W2) R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only R/W R/W R/W R/W R/W R/W R/W
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
LINSCI
SPI
ITC
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Address 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh
Block FLASH
Register Label FSCR WWDGCR
Register Name Flash Control/Status Register Window Watchdog Control Register Window Watchdog Window Register Main Clock Control / Status Register Main Clock Controller: Beep Control Register
Reset Status 00h 7Fh 7Fh 00h 00h 00h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h
Remarks R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
WATCHDOG WWDGWR MCC MCCSR MCCBCR
ADC
Control/Status Register ADCCSR ADCDRMSB Data Register MSB ADCDRLSB Data Register LSB TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR SICSR TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register System Integrity Control/Status Register Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register
TIMER A
SIM
000x000x b R/W 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
TIMER B
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Address 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h to 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h
Block
Register Label MTIM MTIML MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MCRC MPHST MDFR MCFR MREF MPCR MREP MCPWH MCPWL MCPVH MCPVL MCPUH MCPUL MCP0H MCP0L MDTG MPOL MPWME MCONF MPAR MZRF MSCR
Register Name Timer Counter High Register Timer Counter Low Register Capture Zn-1 Register Capture Zn Register Compare Cn+1 Register Demagnetization Register An Weight Register Prescaler & Sampling Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Control Register C Phase State Register D event Filter Register Current feedback Filter Register Reference Register PWM Control Register Repetition Counter Register Compare Phase W Preload Register High Compare Phase W Preload Register Low Compare Phase V Preload Register High Compare Phase V Preload Register Low Compare Phase U Preload Register High Compare Phase U Preload Register Low Compare Phase 0 Preload Register High Compare Phase 0 Preload Register Low Dead Time Generator Enable Polarity Register PWM Register Configuration Register Parity Register Z event Filter Register Sampling Clock Register Reserved Area (4 Bytes)
Reset Status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0Fh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0Fh FFh FFh 3Fh 00h 02h 00h 0Fh 00h
Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MTC (page 0)
MTC (page 1)
see MTC description
DM
DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L
Debug Control Register Debug Status Register Debug Breakpoint 1 MSB Register Debug Breakpoint 1 LSB Register Debug Breakpoint 2 MSB Register Debug Breakpoint 2 LSB Register
00h 10h FFh FFh FFh FFh
R/W Read Only R/W R/W R/W R/W
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Address 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
Block
Register Label PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR PWM AR PWM AR PWM AR PWM AR PWM AR
Register Name Timer Duty Cycle Register Timer Duty Cycle Register Timer Duty Cycle Register Timer Duty Cycle Register Timer Control Register 3 2 1 0
Reset Status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W
PWM ART
ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2
Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register AR Timer Input Capture Control/Status Reg. AR Timer Input Capture Register 1 AR Timer Input Capture Register 2 OPAMP Control/Status Register
OPAMP
OACSR
Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
s
Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 9). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 3. Sectors available in Flash devices
Flash Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
s
s s
Three Flash programming modes: - Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. - ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. - IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection against piracy Register Access Security System (RASS) to prevent accidental programming or erasing
4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Figure 9. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
4.3.1 Read-out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: - In Flash devices it is enabled and removed through the FMP_R bit in the option byte. - In ROM devices it is enabled by mask option specified in the Option List.
8K
10K
16K
24K
32K
48K
60K
FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
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FLASH PROGRAM MEMORY (Cont'd) 4.4 ICC Interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 10). These pins are: - RESET: device reset - VSS: device power supply ground Figure 10. Typical ICC Interface
PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) OPTIONAL (See Note 4) ICC CONNECTOR HE10 CONNECTOR TYPE 9 10 7 8 5 6 3 4 1 2 APPLICATION RESET SOURCE See Note 2 10k APPLICATION POWER SUPPLY CL2 CL1 See Note 1 APPLICATION I/O
- - - -
ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) - VDD: application board power supply (optional, see Figure 10, Note 3)
RESET
ST7
Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values. 2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-
agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.
ICCSEL/VPP
ICCDATA
ICCCLK
OSC2
OSC1
VDD
VSS
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FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 10). For more details on the pin locations, refer to the device pinout description. 4.6 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. 4.8 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.
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5 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11. For more details, refer to dedicated parametric section.
s s s
Reset Sequence Manager (RSM) 1 Crystal/Ceramic resonator oscillator System Integrity Management (SI) - Main supply Low voltage detection (LVD) - Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply - Clock Security System (CSS) with the VCO of the PLL, providing a backup safe oscillator - Clock Detector - PLL which can be used to multiply the frequency by 2 if the clock frequency input is 8MHz
Main features Figure 11. Clock, Reset and Supply Block Diagram
SYSTEM INTEGRITY MANAGEMENT
fOSC CLOCK SECURITY SYSTEM 8Mhz OSCILLATOR OSC1 fOSC DIV2 OPT CKSEL fCLK fCPU MAIN CLOCK CONTROLLER WITH REALTIME fMTC CLOCK (MCC/RTC)
OSC2
PLL
Safeosc
16Mhz
lock
1/2
SICSR, page 1 PA GE 0 VCO LO PLL EN CK EN 0 CK SEL 0
Clock Detector
RESET SEQUENCE RESET MANAGER (RSM) SICSR, page 0
AVD Interrupt Request PA AVD AVD LVD GE IE F RF CSS CSS WDG IE D RF
WATCHDOG TIMER (WDG)
0
CSS Interrupt Request LOW VOLTAGE VSS VDD DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
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5.1 OSCILLATOR The main clock of the ST7 can be generated by a crystal or ceramic resonator oscillator or an external source. The associated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is not connected. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. In this mode, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. This oscillator is not stopped during the RESET phase to avoid losing time in its start-up phase. See Electrical Characteristics for more details. Table 4. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OSC1 OSC2 NC EXTERNAL SOURCE
Crystal/Ceramic Resonators
ST7 OSC1 OSC2
CL1
LOAD CAPACITORS
CL2
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5.2 RESET SEQUENCE MANAGER (RSM) 5.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 13: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 12: s Active Phase depending on the RESET source s 256 or 4096 CPU clock cycle delay (selected by option byte) s RESET vector fetch The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. Figure 13. Reset Block Diagram The RESET vector fetch phase duration is 2 clock cycles. Figure 12. RESET Sequence Phases
RESET
Active Phase INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR
5.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 14). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
VDD
RON
RESET
Filter INTERNAL RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 5.2.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 5.2.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDFigure 14. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
LVD RESET
EXTERNAL RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH
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5.3 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) and Clock Security System (CSS) functions. It is managed by the SICSR register. 5.3.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling Figure 15. Low Voltage Detector vs Reset
VDD
The LVD function is illustrated in Figure 15. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: - under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be selected by option byte.
Vhys VIT+ VIT-
RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 5.3.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply. The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD function is active only if the LVD is enabled through the option byte (see section 13.1 on page 284). 5.3.2.1 Monitoring the VDD Main Supply If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 16. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: - If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. - If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.
Figure 16. Using the AVD to Monitor VDD VDD Early Warning Interrupt (Power has dropped, MCU not not yet in reset)
Vhyst
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
trv VOLTAGE RISE TIME
AVDF bit AVD INTERRUPT REQUEST IF AVDIE bit = 1
0
1
0
INTERRUPT PROCESS
INTERRUPT PROCESS
LVD RESET
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 5.3.3 Clock Security System (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a PLL which can provide a backup clock. The PLL can be enabled or disabled by option byte or by software. It requires an 8-MHz input clock and provides a 16-MHz output clock. 5.3.3.1 Safe Oscillator Control The safe oscillator of the CSS block is made of a PLL. If the clock signal disappears (due to a broken or disconnected resonator...) the PLL continues to provide a lower frequency, which allows the ST7 to perform some rescue operations. Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers. 5.3.3.2 Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the SICSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the SICSR register description. 5.3.4 Low Power Modes
Mode WAIT Description No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode. The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. The AVD remains active, and an AVD interrupt can be used to exit from Halt mode.
HALT
5.3.4.1 Interrupts The CSS or AVD interrupt events generate an interrupt if the corresponding Enable Control Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event Enable Event Control Flag Bit CSSIE AVDIE Exit from Wait Yes Yes Exit from Halt No 1) Yes
CSS event detection (safe oscillator acti- CSSD vated as main clock) AVD event AVDF
Note 1: This interrupt allows to exit from activehalt mode.
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) 5.3.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0) Read /Write is detected by the Clock Security System (CSSD bit set). It is set and cleared by software. Reset Value: 000x 000x (00h) 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled 7 0 When the PLL is disabled (PLLEN=0), the CSSIE bit has no effect. AVD AVD LVD PAG CSS CSS WDG
E IE F RF 0 IE D RF
Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR register page. It is set and cleared by software 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the VDIE bit is set, an interrupt request is generated when the AVDF bit changes value. 0: VDD over VIT+ (AVD) threshold 1: VDD under VIT-(AVD) threshold Bit 4 = LVDRF LVD reset flag This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 3 = Reserved, must be kept cleared. Bit 2 = CSSIE Clock security syst. interrupt enable This bit enables the interrupt when a disturbance
Bit 1 = CSSD Clock security system detection This bit indicates a disturbance on the main clock signal (fOSC): the clock stops (at least for a few cycles). It is set by hardware and cleared by reading the SICSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the PLL is disabled (PLLEN=0), the CSSD bit value is forced to 0. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
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SYSTEM INTEGRITY MANAGEMENT (Cont'd) SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1) Reset Value: 00000000 (00h) Bit 3 = PLLEN PLL Enable This bit enables the PLL and the clock detector. It is set and cleared by software. 7 0 0: PLL and Clock Detector (CKD) disabled VCO LO PLL PA CK1: PLL and Clock Detector (CKD) enabled 0 0 0
GE EN CK EN SEL
Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR register page. It is set and cleared by software 0: Access to SICSR register mapped in page 0. 1: Access to SICSR register mapped in page 1. Bit 6 = Reserved, must be kept cleared. Bit 5 = VCOEN VCO Enable This bit is set and cleared by software. 0: VCO (Voltage Controlled Oscillator) connected to the output of the PLL charge pump (default mode), to obtain a 16-MHz output frequency (with an 8-MHz input frequency). 1: VCO tied to ground in order to obtain a 10-MHz frequency (fvco) Notes: 1. During ICC session, this bit is set to 1 in order to have an internal frequency which does not depend on the input clock. Then, it can be reset in order to run faster with an external oscillator. Bit 4 = LOCK PLL Locked This bit is read only. It is set by hardware. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked
Notes: 1. During ICC session, this bit is set to 1. 2. PLL cannot be disabled if PLL clock source is selected (CKSEL= 1). Bit 2 = Reserved, must be kept cleared. Bit 1 = CKSELClock Source Selection This bit selects the clock source: oscillator clock or clock from the PLL. It is set and cleared by software. It can also be set by option byte (PLL opt) 0: Oscillator clock selected 1: PLL clock selected Notes: 1. During ICC session, this bit is set to 1. Then, CKSEL can be reset in order to run with fOSC. 2. Clock from the PLL cannot be selected if the PLL is disabled (PLLEN =0) 3. If the clock source is selected by PLL option bit, CKSEL bit selection has no effect. Bit 0 = Reserved, must be kept cleared.
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5.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three different functions: s a programmable CPU clock prescaler s a clock-out signal to supply external devices s a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 5.4.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See Section 7.2 SLOW MODE for more details). The prescaler selects the fCPU main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS. 5.4.2 Clock-out Capability The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC2 clock to drive external devices. It is controlled by the MCO bit in the MCCSR register. CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode. 5.4.3 Real Time Clock Timer (RTC) The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on fOSC2 are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF. When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the HALT instruction is executed. See Section 7.4 ACTIVE-HALT AND HALT MODES for more details. 5.4.4 Beeper The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function).
Figure 17. Main Clock Controller (MCC/RTC) Block Diagram
BC1 BC0 MCCBCR BEEP BEEP SIGNAL GENERATOR MCO
DIV128 MCCSR MCO fCLK DIV 2 fOSC2 DIV 2, 4, 8, 16
RTC COUNTER
CP0 SMS TB1 TB0
OIE
OIF MCC/RTC INTERRUPT (AND TO MTC PERIPHERAL) fCPU CPU CLOCK TO CPU AND PERIPHERALS TO MOTOR CONTROL PERIPHERAL
DIV 2 DIV 2, 4, 8, 16
fADC fMTC
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) 5.4.5 Low Power Modes
Mode WAIT Description No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode. MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with "exit from HALT" capability.
Bit 6:5 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
fCPU in SLOW mode fOSC2 / 2 fOSC2 / 4 fOSC2 / 8 fOSC2 / 16 CP1 0 0 1 1 CP0 0 1 0 1
ACTIVEHALT
HALT
5.4.6 Interrupts The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event Time base overflow event Enable Event Control Flag Bit OIF OIE Exit from Wait Yes Exit from Halt No 1)
Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See Section 7.2 SLOW MODE and Section 5.4 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) for more details. Bit 3:2 = TB[1:0] Time base control These bits select the programmable divider time base. They are set and cleared by software.
Time Base Counter Prescaler f OSC2 =4MHz fOSC2=8MHz 16000 4ms 8ms 20ms 50ms 2ms 4ms 10ms 25ms 32000 80000 200000 TB1 0 0 1 1 TB0 0 1 0 1
Note: The MCC/RTC interrupt wakes up the MCU from ACTIVE-HALT mode, not from HALT mode.
5.4.7 Register Description MCC CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0000 (00h)
7 MCO CP1 CP0 SMS TB1 TB0 OIE 0 OIF
A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVEHALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode.
Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fOSC2on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont'd) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. MCC BEEP CONTROL REGISTER (MCCBCR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 ADSTS ADC IE BC1 0 BC0
Bit 7:4 = Reserved, must be kept cleared. Bit 3 = ADSTS A/D Converter Sample Time Stretch This bit is set and cleared by software to enable or disable the A/D Converter sample time stretch feature. 0: AD sample time stretch disabled (for standard impedance analog inputs) 1 AD sample time stretch enabled (for high impedance analog inputs) Bit 2 = ADCIE A/D Converter Interrupt Enable This bit is set and cleared by software to enable or disable the A/D Converter interrupt. 0: AD Interrupt disabled 1 AD Interrupt enabled Bit 1:0 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability.
BC1 0 0 1 1 BC0 0 1 0 1 ~2-KHz ~1-KHz ~500-Hz Beep mode with fOSC2=8MHz Off Output Beep signal ~50% duty cycle
The beep output signal is available in ACTIVEHALT mode but has to be disabled to reduce the consumption. Table 5. Main Clock Controller Register Map and Reset Values
Address (Hex.) 0040h 0040h 002Ch 002Dh Register Label SICSR, page0 Reset Value SICSR, page1 Reset Value MCCSR Reset Value MCCBCR Reset Value 7 PAGE 0 PAGE 0 MCO 0 0 6 VDIE 0 0 CP1 0 0 5 VDF 0 VCOEN 0 CP0 0 0 4 LVDRF x LOCK x SMS 0 0 3 2 CFIE 0 0 TB0 0 ADCIE 0 1 CSSD 0 CKSEL 0 OIE 0 BC1 0 0 WDGRF x 0 OIF 0 BC0 0
0 PLLEN 0 TB1 0 ADSTS 0
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6 INTERRUPTS
6.1 INTRODUCTION The ST7 enhanced interrupt management provides the following features: s Hardware interrupts s Software interrupt (TRAP) s Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 2 non maskable events: RESET, TRAP - 1 maskable top level event: MCES This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 6.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of Figure 18. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y MCES Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
each interrupt vector (see Table 6). The processing flow is shown in Figure 18 When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 6. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 19 describes this decision process. Figure 19. Priority Decision Process
PENDING INTERRUPTS
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 18 as a MCES top level interrupt. RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
s
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and MCES can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 18). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode. s TRAP (Non Maskable Software Interrupt)
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. s MCES (MTC Emergency Stop) This hardware interrupt occurs when a specific edge is detected on the dedicated MCES pin or when an error is detected by the micro in the motor speed measurement. s External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. s Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 6.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 19. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 20. Concurrent Interrupt Management
MCES SOFTWARE PRIORITY LEVEL IT2 IT1 IT4 IT3 IT0
6.4 CONCURRENT & NESTED MANAGEMENT The following Figure 20 and Figure 21 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 21. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, MCES. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
I1
I0
HARDWARE PRIORITY
MCES IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 21. Nested Interrupt Management
MCES
SOFTWARE PRIORITY LEVEL
IT2
IT1
IT4
IT3
IT0
I1
I0
HARDWARE PRIORITY
MCES IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 6.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read /Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: MCES, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
- Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and MCES vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the MCES can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd)
Table 7. Dedicated Interrupt Instruction Set
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 (level 3) Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.
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INTERRUPTS (Cont'd) Table 8. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SPI TIMER A TIMER B LINSCI AVD/ ADC PWM ART MTC MCES MCC/RTC CSS ei0 ei1 ei2 Reset Software interrupt Motor Control Emergency Stop or Speed error interrupt Main clock controller time base interrupt Safe oscillator activation interrupt External interrupt port External interrupt port External interrupt port Event U or Current Loop or Sampling Out Event R or Event Z Event C or Event D SPI peripheral interrupts TIMER A peripheral interrupts TIMER B peripheral interrupts LINSCI Peripheral interrupts Auxiliary Voltage detector interrupt ADC End of conversion interrupt PWM ART overflow interrupt SPICSR TASR TBSR SCISR SICSR ADCSR ARTCSR Lowest Priority MISR N/A Description Register Label N/A MISR MCRC MCCSR SICSR Highest Priority Priority Order Exit from HALT1) yes no no yes yes yes yes no no no yes no no no yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from ACTIVE-HALT mode only.
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INTERRUPTS (Cont'd) 6.6 EXTERNAL INTERRUPTS The pending interrupts are cleared writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Note: External interrupts are masked when an I/O (configured as input interrupt) of the same interrupt vector is forced to VSS. 6.6.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows to have up to 4 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level s Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3).
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INTERRUPTS (Cont'd) Figure 22. External Interrupt Control bits
PORT D [6:4] INTERRUPTS PDOR.6 PDDDR.6 PD6 CONTROL IPA BIT PD5 PD4 EICR IS30 IS31 PD6 ei0 INTERRUPT SOURCE
SENSITIVITY
PORT D [3:1] INTERRUPTS PDOR.3 PDDDR.3 PD3
EICR IS30 IS31 PD3 PD2 PD1
SENSITIVITY CONTROL
ei0 INTERRUPT SOURCE
PORT A [7:3] INTERRUPTS PAOR.7 PADDR.7 PA7
EICR IS20 IS21 PA7 PA6 PA5 PA3
SENSITIVITY CONTROL
ei1 INTERRUPT SOURCE
PORT C [3:1] INTERRUPTS PCOR.3 PCDDR.3 PC3
EICR IS10 IS11 PC3 PC2 PC1
SENSITIVITY CONTROL
ei2 INTERRUPT SOURCE
IPB BIT
PORT C0, PB[7:6] INTERRUPTS PCOR.0 PCDDR.0 PC0
EICR IS10 IS11 PC0 PB7 PB6
SENSITIVITY CONTROL
ei2 INTERRUPT SOURCE
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INTERRUPTS (Cont'd) 6.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read /Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 IPB IS21 IS20 IS31 IS30 0 IPA
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = IPB Interrupt polarity for port C This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion Bit 4:3= IS2[1:0] ei1sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei1 (port A3, A5...A7)
IS21 IS20 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bit 7:6 = IS1[1:0] ei2 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port C3..1)
External Interrupt Sensitivity IS11 IS10 IPB bit =0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPB bit =1 Rising edge & high level Falling edge only Rising edge only
Rising and falling edge
- ei2 (port C0, B7..6)
IS11 IS10 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Bit 2:1= IS3[1:0] ei0sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:
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EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont'd) - ei0 (port D5..3)
External Interrupt Sensitivity IS31 IS30 IPA bit =0 0 0 1 1 0 1 0 1 Falling edge & low level Rising edge only Falling edge only IPA bit =1 Rising edge & high level Falling edge only Rising edge only
Bit 0= IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion
Rising and falling edge
- ei0 (port D2..0)
IS31 IS30 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).
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INTERRUPTS (Cont'd) Table 9. Nested Interrupts Register Map and Reset Values
Address (Hex.) 0024h Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value EICR Reset Value 7 ei1 I1_3 I0_3 1 1 MTC C/D I1_7 I0_7 1 1 SCI 0026h I1_11 1 I1_15 1 IS11 0 I0_11 1 I0_15 1 IS10 0 6 5 ei0 I1_2 I0_2 1 1 MTC R/Z I1_6 I0_6 1 1 TIMER B I1_10 I0_10 1 1 I1_14 1 IPB 0 I0_14 1 IS21 0 4 3 MCC + SI I1_1 I0_1 1 1 MTC U/CL I1_5 I0_5 1 1 TIMER A I1_9 I0_9 1 1 PWMART I1_13 1 IS20 0 I0_13 1 IPA 0 1 ei2 I1_4 1 SPI I1_8 1 AVD I1_12 1 0 I0_12 1 0 I0_8 1 I0_4 1 2 1 MCES 1 0
0025h
0027h 0028h
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7 POWER SAVING MODES
7.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 23): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (fOSC2). From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 23. Power Saving Mode Transitions Figure 24. SLOW Mode Clock Transitions
High
fOSC2/2 fOSC2/4 fOSC2
7.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in SLOW mode.
RUN SLOW MCCSR WAIT SLOW WAIT ACTIVE HALT HALT Low POWER CONSUMPTION
fCPU
fOSC2 CP1:0 SMS 00 01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 7.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the `WFI' instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to `10', to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 25. Figure 25. WAIT Mode Flow-chart
OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 10
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 Y
256 OR 4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I[1:0] BITS
ON ON ON XX 1)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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POWER SAVING MODES (Cont'd) 7.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the `HALT' instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR OIE bit 0 1 Power Saving Mode entered when HALT instruction is executed HALT mode ACTIVE-HALT mode HALT INSTRUCTION (MCCSR.OIE=1)
Figure 26. ACTIVE-HALT Timing Overview
RUN ACTIVE HALT 256 OR 4096 CPU CYCLE DELAY 1) RESET OR INTERRUPT RUN
HALT INSTRUCTION [MCCSR.OIE=1]
FETCH VECTOR
Figure 27. ACTIVE-HALT Mode Flow-chart
OSCILLATOR ON PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 10 N RESET N INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON XX 4) Y
7.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see section 5.4 on page 32 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see Table 8, "Interrupt Mapping," on page 40) or a RESET. When exiting ACTIVEHALT mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 27). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to `10b' to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVEHALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.
256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX 4)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Notes: 1. This delay occurs only if the MCU exits ACTIVEHALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 8, "Interrupt Mapping," on page 40 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.
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POWER SAVING MODES (Cont'd) 7.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the `HALT' instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 5.4 on page 32 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 8, "Interrupt Mapping," on page 40) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 29). When entering HALT mode, the I[1:0] bits in the CC register are forced to `10b'to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see section 13.1 on page 284 for more details). Figure 28. HALT Timing Overview
RUN HALT 256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT FETCH VECTOR FETCH RESET VECTOR OR SERVICE INTERRUPT RUN
Figure 29. HALT Mode Flow-chart
HALT INSTRUCTION (MCCSR.OIE=0) ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I[1:0] BITS 10 0 WATCHDOG DISABLE
N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON XX 4)
256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON ON XX 4)
HALT INSTRUCTION [MCCSR.OIE=0]
Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 8, "Interrupt Mapping," on page 40 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.
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8 I/O PORTS
8.1 INTRODUCTION The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 30 8.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed. The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified. 8.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain Vss Floating
8.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont'd) Figure 30. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONDITION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 10. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
DATA BUS
DR SEL
1 0
ALTERNATE INPUT
NI (see note)
Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
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I/O PORTS (Cont'd) Table 11. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONDITION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (ei x) INTERRUPT CONDITION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT 2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 8.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 31 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 31. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
8.4 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
8.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Yes Exit from Halt Yes
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I/O PORTS (Cont'd) 8.5.1 I/O Port Implementation The I/O port register configurations are summarised as follows. Standard Ports PA4, PA2:0, PB5:0, PC7:4, PD7:6, PE5:0, PF5:0, PG7:0, PH7:0
MODE floating input pull-up input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
Interrupt Ports PA6, PA3, PB6, PC3, PC1, PD5, PD4, PD2 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
PA7, PA5, PB7, PC2, PC0, PD6, PD3, PD1 (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
Table 12. Port Configuration
Port Pin name
PA7, PA5
Input OR = 0
floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating floating
Output OR = 1
floating interrupt pull-up interrupt pull-up floating interrupt pull-up interrupt pull-up pull-up pull-up interrupt floating interrupt pull-up floating interrupt pull-up interrupt pull-up pull-up pull-up pull-up
OR = 0
open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain
OR = 1
push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull
Port A
PA6, PA3 PA2:0 PB7 PB6 PB5:0 PC7:4
Port B
Port C
PC3, PC1 PC2, PC0 PD7, PD0 PD6, PD3, PD1 PD5, PD4, PD2 PE5:0 PF5:0 PG7:0 PH7:0
Port D Port E Port F Port G Port H
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I/O PORTS (Cont'd) Table 13. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Reset Value of all I/O port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h PDDR 000Ah PDDDR 000Bh PDOR 000Ch PEDR 000Dh PEDDR 000Eh PEOR 000Fh PFDR 0010h PFDDR 0011h PFOR 0012h PGDR 0013h PGDDR 0014h PGOR 0015h PHDR 0016h PHDDR 0017h PHOR
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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9 ON-CHIP PERIPHERALS
9.1 WINDOW WATCHDOG (WWDG) 9.1.1 Introduction The Window Watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. 9.1.2 Main Features - Programmable free-running downcounter - Conditional reset - Reset (if watchdog activated) when the downcounter value becomes less than 40h - Reset (if watchdog activated) if the downFigure 32. Watchdog Block Diagram
RESET W6 WATCHDOG WINDOW REGISTER (WDGWR) W5 W4 W3 W2 W1 W0
counter is reloaded outside the window (see Figure 35) - Hardware/Software Watchdog activation (selectable by option byte) - Optional reset on HALT instruction (configurable by option byte) 9.1.3 Functional Description The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0] bits) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30s. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.
comparator =1 when T6:0 > W6:0 CMP Write WDGCR WATCHDOG CONTROL REGISTER (WDGCR) WDGA T6 T5 T4 T3 T2 T1 T0
MCC/RTC fOSC2
DIV 64
6-BIT DOWNCOUNTER (CNT)
WDG PRESCALER DIV 4 12-BIT MCC RTC COUNTER MSB
11 65
LSB
0
TB[1:0] bits (MCCSR Register)
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WINDOW WATCHDOG (Cont'd) The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WDGCR register must be between FFh and C0h (see Figure 33): - Enabling the watchdog: When Software Watchdog is selected (by option byte), the watchdog is disabled after a reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be disabled again except by a reset. When Hardware Watchdog is selected (by option byte), the watchdog is always active and the WDGA bit is not used. - Controlling the downcounter : This downcounter is free-running: it counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 33. Approximate Timeout Duration). The timing varies
between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see Figure 34). The window register (WDGWR) contains the high limit of the window: to prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3Fh. Figure 35 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). - Watchdog Reset on Halt option If the watchdog is activated and the watchdog reset on halt option is selected, then the HALT instruction will generate a Reset. 9.1.4 Using Halt Mode with the WDG If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
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WINDOW WATCHDOG (Cont'd) 9.1.5 How to Program the Watchdog Timeout Figure 33 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If Figure 33. Approximate Timeout Duration 3F 38
more precision is needed, use the formulae in Figure 34. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.
30
CNT Value (hex.)
28
20 18
10
08 00 1.5 18 34 50 65 82 98 114 128 Watchdog timeout (ms) @ 8 MHz. fOSC2
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WATCHDOG TIMER (Cont'd) Figure 34. Exact Timeout Duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2=8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register
TB1 Bit TB0 Bit (MCCSR Reg.) (MCCSR Reg.) 0 0 0 1 1 0 1 1 Selected MCCSR Timebase 2ms 4ms 10ms 25ms MSB 4 8 20 49 LSB 59 53 35 54
To calculate the minimum Watchdog Timeout (tmin): IF CNT < MSB ------------4
THEN t min = t m in0 + 16384 x CNT x t osc2 ELSE t min = tm in0 + 16384 x CN T - 4 CNT + ( 192 + L SB ) x 64 x 4CNT ------------------------------ MSB MSB
x tosc2
To calculate the maximum Watchdog Timeout (tmax): IF CNT MSB ------------4
THEN t max = t m ax0 + 16384 x CNT x t osc2 ELSE t
max 4CNT =t + 16384 x C NT - ---------------- m ax0 MSB
+ ( 192 + LSB ) x 64 x
4CNT ---------------MS B
x to sc2
Note: In the above formulae, division results must be rounded down to the next integer value. Example: With 2ms timeout selected in MCCSR register
Value of T[5:0] Bits in WDGCR Register (Hex.) 00 3F Min. Watchdog Timeout (ms) tmin 1.496 128 Max. Watchdog Timeout (ms) tmax 2.048 128.552
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WINDOW WATCHDOG (Cont'd) Figure 35. Window Watchdog Timing Diagram
T[5:0] CNT downcounter
WDGWR
3Fh
Refresh not allowed Refresh Window
time (step = 16384/fOSC2)
T6 bit Reset
9.1.6 Low Power Modes Mode SLOW WAIT Description No effect on Watchdog : the downcounter continues to decrement at normal speed. No effect on Watchdog : the downcounter continues to decrement.
OIE bit in MCCSR register WDGHALT bit in Option Byte No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset. 0 0 If an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see Section 9.1.8 below. A reset is generated instead of entering halt mode. No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.
HALT
0
1
ACTIVE HALT
1
x
9.1.7 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description.
9.1.8 Using Halt Mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
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WINDOW WATCHDOG (Cont'd) 9.1.9 Interrupts None. 9.1.10 Register Description CONTROL REGISTER (WDGCR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB). These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). WINDOW REGISTER (WDGWR) Read/Write Reset Value: 0111 1111 (7Fh)
7 W6 W5 W4 W3 W2 W1 0 W0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled
Bit 7 = Reserved Bits 6:0 = W[6:0] 7-bit window value These bits contain the window value to be compared to the downcounter.
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Table 14. Watchdog Timer Register Map and Reset Values
Address (Hex.) 002Ah 002Bh Register Label WDGCR Reset Value WDGWR Reset Value 7 WDGA 0 0 0 6 T6 1 W6 1 5 T5 1 W5 1 4 T4 1 W4 1 3 T3 1 W3 1 2 T2 1 W2 1 1 T1 1 W1 1 0 T0 1 W0 1
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9.2 PWM AUTO-RELOAD TIMER (ART) 9.2.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: - Generation of up to 4 independent PWM signals - Output compare and Time base interrupt Figure 36. PWM Auto-Reload Timer Block Diagram
PWMCR OEx OPx OCRx REGISTER LOAD PWMx PORT ALTERNATE FUNCTION POLARITY CONTROL COMPARE DCRx REGISTER
- Up to two input capture functions - External event detector - Up to two external interrupt sources The three first modes can be used together with a single counter frequency. The timer can be used to wake up the MCU from WAIT and HALT modes.
ARR REGISTER
8-BIT COUNTER (CAR REGISTER)
LOAD
ARTICx
INPUT CAPTURE CONTROL
LOAD
ICRx REGISTER
ICSx
ICIEx
ICFx
ICCSR
ARTCLK
fEXT fCPU fCOUNTER
ICx INTERRUPT
MUX fINPUT
PROGRAMMABLE PRESCALER
EXCL
CC2
CC1
CC0
TCE
FCRL
OIE
OVF
ARTCSR
OVF INTERRUPT
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PWM AUTO-RELOAD TIMER (Cont'd) 9.2.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected). Counter clock and prescaler The counter clock frequency is given by: fCOUNTER = fINPUT / 2CC[2:0] The timer counter's input clock (fINPUT) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7). This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and can be either the fCPU or an external input frequency fEXT. The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source. Figure 37. Output compare control Counter and Prescaler Initialization After RESET, the counter and the prescaler are cleared and fINPUT = fCPU. The counter can be initialized by: - Writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR register. - Writing to the ARTCAR counter access register, In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. Direct access to the prescaler is not possible. Output compare control The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made between the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cycle register (PWMDCRx) at each overflow of the counter. This double buffering method avoids glitch generation when changing the duty cycle on the fly.
fCOUNTER ARTARR=FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh FFh
OCRx
FDh
FEh
PWMDCRx
FDh
FEh
PWMx
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PWM AUTO-RELOAD TIMER (Cont'd) Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function. The PWM signals all have the same frequency which is controlled by the counter period and the ARTARR register value. fPWM = fCOUNTER / (256 - ARTARR) When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register. Figure 38. PWM Auto-reload Timer Function
255 DUTY CYCLE REGISTER (PWMDCRx)
When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored. It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARTARR register. The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARTARR) Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.
COUNTER
AUTO-RELOAD REGISTER (ARTARR) 000
t
PWMx OUTPUT
WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1
Figure 39. PWM Signal from 0% to 100% Duty Cycle
fCOUNTER ARTARR=FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh
OCRx=FCh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh
t
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PWM AUTO-RELOAD TIMER (Cont'd) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application. External clock and event detector mode Using the fEXT external prescaler input clock, the auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register is used to select the nEVENT number of events to be counted before setting the OVF flag. nEVENT = 256 - ARTARR Caution: The external clock function is not available in HALT mode. If HALT mode is used in the application, prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the ARTCSR register to avoid spurious counter increments.
Figure 40. External Event Detector Example (3 counts)
f EXT=fCOUNTER ARTARR=FDh
COUNTER
FDh
FEh
FFh
FDh
FEh
FFh
FDh
OVF
ARTCSR READ INTERRUPT IF OIE=1 INTERRUPT IF OIE=1
ARTCSR READ
t
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PWM AUTO-RELOAD TIMER (Cont'd) Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR). These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register. The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register. The read only input capture registers (ARTICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register). After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. Note: After a capture detection, data transfer in the ARTICRx register is inhibited until it is read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit set). This means, the ARTICRx register has to be read at each capture event to clear the CFx flag. The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER). Note: During HALT mode, if both input capture and external clock are enabled, the ARTICRx register value is not guaranteed if the input capture pin and the external clock change simultaneously. Figure 41. Input Capture Timing Diagram
fCOUNTER
External interrupt capability This mode allows the Input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR register) and they are independently enabled through CIEx bits of the ARTICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source. During HALT mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set).
COUNTER
01h
02h
03h
04h
05h
06h
07h
ARTICx PIN CFx FLAG xxh ICRx REGISTER
INTERRUPT
04h
t
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PWM AUTO-RELOAD TIMER (Cont'd) 9.2.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read /Write Reset Value: 0000 0000 (00h)
7 EXCL CC2 CC1 CC0 TCE FCRL OIE 0 OVF 7 0 CA6 CA5 CA4 CA3 CA2 CA1 CA0
0: New transition not yet reached 1: Transition reached COUNTER ACCESS REGISTER (ARTCAR) Read /Write Reset Value: 0000 0000 (00h)
Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from fINPUT.
fCOUNTER fINPUT fINPUT / 2 fINPUT / 4 fINPUT / 8 fINPUT / 16 fINPUT / 32 fINPUT / 64 fINPUT / 128 With fINPUT=8 MHz CC2 CC1 CC0 8 MHz 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CA7
Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hardware or by software. The ARTCAR register is used to read or write the auto-reload counter "on the fly" (while it is counting).
AUTO-RELOAD REGISTER (ARTARR) Read /Write Reset Value: 0000 0000 (00h)
7 AR7 AR6 AR5 AR4 AR3 AR2 AR1 0 AR0
Bit 3 = TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running. Bit 2 = FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Bit 1 = OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable. Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value.
Bit 7:0 = AR[7:0] Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register has two PWM management functions: - Adjusting the PWM frequency - Setting the PWM duty cycle resolution PWM Frequency vs. Resolution:
ARTARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] Resolution Min 8-bit > 7-bit > 6-bit > 5-bit > 4-bit ~0.244-KHz ~0.244-KHz ~0.488-KHz ~0.977-KHz ~1.953-KHz fPWM Max 31.25-KHz 62.5-KHz 125-KHz 250-KHz 500-KHz
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PWM AUTO-RELOAD TIMER (Cont'd) PWM CONTROL REGISTER (PWMCR) Read /Write Reset Value: 0000 0000 (00h)
7 OE3 OE2 OE1 OE0 OP3 OP2 OP1 0 OP0
DUTY CYCLE REGISTERS (PWMDCRx) Read /Write Reset Value: 0000 0000 (00h)
7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0
Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:0 = OP[3:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the four PWM output signals.
PWMx output level OPx Counter <= OCRx 1 0 Counter > OCRx 0 1 0 1
Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software. A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR registers allow the duty cycle to be set independently for each PWM channel.
Note: When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
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PWM AUTO-RELOAD TIMER (Cont'd) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 CS2 CS1 CIE2 CIE1 CF2 0 IC7 CF1 IC6 IC5 IC4 IC3 IC2 IC1 IC0
INPUT CAPTURE REGISTERS (ARTICRx) Read only Reset Value: 0000 0000 (00h)
7 0
Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x. 1: Rising edge triggers capture on channel x. Bit 3:2 = CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software. They enable or disable the Input capture channel interrupts independently. 0: Input capture channel x interrupt disabled. 1: Input capture channel x interrupt enabled. Bit 1:0 = CF[2:1] Capture Flag These bits are set by hardware and cleared by software reading the corresponding ARTICRx register. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x. 1: An input capture has occured on channel x.
Bit 7:0 = IC[7:0] Input Capture Data These read only bits are set and cleared by hardware. An ARTICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event.
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PWM AUTO-RELOAD TIMER (Cont'd) Table 15. PWM Auto-Reload Timer Register Map and Reset Values
Address (Hex.) 0073h Register Label PWMDCR3 Reset Value PWMDCR2 Reset Value PWMDCR1 Reset Value PWMDCR0 Reset Value PWMCR Reset Value ARTCSR Reset Value ARTCAR Reset Value ARTARR Reset Value ARTICCSR Reset Value ARTICR1 Reset Value ARTICR2 Reset Value 0 IC7 0 IC7 0 0 IC6 0 IC6 0 7 DC7 0 DC7 0 DC7 0 DC7 0 OE3 0 EXCL 0 CA7 0 AR7 0 6 DC6 0 DC6 0 DC6 0 DC6 0 OE2 0 CC2 0 CA6 0 AR6 0 5 DC5 0 DC5 0 DC5 0 DC5 0 OE1 0 CC1 0 CA5 0 AR5 0 CS2 0 IC5 0 IC5 0 4 DC4 0 DC4 0 DC4 0 DC4 0 OE0 0 CC0 0 CA4 0 AR4 0 CS1 0 IC4 0 IC4 0 3 DC3 0 DC3 0 DC3 0 DC3 0 OP3 0 TCE 0 CA3 0 AR3 0 CIE2 0 IC3 0 IC3 0 2 DC2 0 DC2 0 DC2 0 DC2 0 OP2 0 FCRL 0 CA2 0 AR2 0 CIE1 0 IC2 0 IC2 0 1 DC1 0 DC1 0 DC1 0 DC1 0 OP1 0 OIE 0 CA1 0 AR1 0 CF2 0 IC1 0 IC1 0 0 DC0 0 DC0 0 DC0 0 DC0 0 OP0 0 OVF 0 CA0 0 AR0 0 CF1 0 IC0 0 IC0 0
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
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ST7MC1/ST7MC2
9.3 16-BIT TIMER 9.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some devices of the ST7 family have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a Device reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In the devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 9.3.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse width modulation mode (PWM) s One pulse mode s Reduced Power Mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 42. *Note: Some timer pins may not available (not bonded) in some devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 9.3.3 Functional Description 9.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 16 Clock Control Bits. The value in the counter register repeats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) Figure 42. Timer Block Diagram
INTERNAL BUS fCPU 16-BIT TIMER PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTURE REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8
8 high
OUTPUT COMPARE CIRCUIT 6
EDGE DETECT CIRCUIT1
ICAP1 pin
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 TIMD
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Control/Status Register) CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See Device Interrupt Vector Table)
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other instructions Read At t0 +t LS Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (Device awakened by an interrupt) or from the reset count (Device awakened by a Reset). 9.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) Figure 43. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 44. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 45. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The Device is in reset state when the internal reset signal is high, when it is low the Device is running.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 9.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 16 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input).
When an input capture occurs: - ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 47). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only the input capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh).
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) Figure 46. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 47. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The active edge is the rising edge. FF03 FF01 FF02 FF03
Note: The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3 CPU clock cycles. This depends on the moment when the ICAP event happens relative to the timer clock.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 9.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCIE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16 Clock Control Bits) fCPU If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 16 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 49 on page 80). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 50 on page 80). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 48. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in both one pulse mode and PWM mode.
16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit
OC1E OC2E
CC1
CC0
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) Figure 49. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 50. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 9.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 16 Clock Control Bits). One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 16 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) = External timer clock frequency (in hertz) fEXT When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 51). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.
OCMP1 = OLVL1
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1 register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin and the ICF1 bit is set. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) Figure 51. One Pulse Mode Timing Example
IC1R COUNTER ICAP1 OCMP1 OLVL2 OLVL1 OLVL2 01F8 FFFC FFFD FFFE 01F8 2ED0 2ED1 2ED2 2ED3 2ED3 FFFC FFFD
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 52. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 9.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are loaded in their respective shadow registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). The shadow registers contain the reference values for comparison in PWM "double buffering" mode. Note: There is a locking mechanism for transferring the OCiR value to the buffer. After a write to the OCiHR register, transfer of the new compare value to the buffer is inhibited until OCiLR is also written. Unlike in Output Compare mode, the compare function is always enabled in PWM mode. Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 16
Clock Control Bits). Pulse Width Modulation cycle When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 16 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 52) Notes: 1. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 2. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 3. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and 9.3.4 Low Power Modes
Mode WAIT
ICF1 can also generates interrupt if ICIE is set. 4. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.
Description No effect on 16-bit Timer. Timer interrupts cause the Device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the Device is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the Device is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the Device is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
9.3.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 9.3.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes Not Recommended1) No Partially 2) 3) Not Recommended No No
See note 4 in Section 9.3.3.5 One Pulse Mode See note 5 in Section 9.3.3.5 One Pulse Mode 3) See note 4 in Section 9.3.3.6 Pulse Width Modulation Mode
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) 9.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 16. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse Mode. 0: One Pulse Mode is not active. 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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ST7MC1/ST7MC2
16-BIT TIMER (Cont'd) CONTROL/STATUS REGISTER (CSR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 0
Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled Bits 1:0 = Reserved, must be kept cleared.
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register.
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16-BIT TIMER (Cont'd) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 17. 16-Bit Timer Register Map and Reset Values
Address (Hex.) Timer A: Timer B: Timer A: Timer B: 32 42 31 41 Register Label CR1 Reset Value CR2 Reset Value 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB MSB MSB MSB MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 1 1 1 1 5 TOIE 0 OPM 0 TOF 0 1 1 1 1 4 FOLV2 0 PWM 0 ICF2 0 1 1 1 1 3 FOLV1 0 CC1 0 OCF2 0 1 1 1 1 2 OLVL2 0 CC0 0 TIMD 0 1 1 1 1 1 IEDG1 0 IEDG2 0 0 1 0 1 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB LSB LSB LSB LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
Timer A: 33 CSR Timer B: 43 Reset Value Timer A: 34 Timer B: 44 Timer A: 35 Timer B: 45 Timer A: 36 Timer B: 46 Timer A: 37 Timer B: 47 Timer A: 3E Timer B: 4E Timer A: 3F Timer B: 4F Timer A: 38 Timer B: 48 Timer A: 39 Timer B: 49 Timer A: 3A Timer B: 4A Timer A: 3B Timer B: 4B Timer A: 3C Timer B: 4C Timer A: 3D Timer B: 4D ICHR1 Reset Value ICLR1 Reset Value OCHR1 Reset Value OCLR1 Reset Value OCHR2 Reset Value OCLR2 Reset Value CHR Reset Value CLR Reset Value ACHR Reset Value ACLR Reset Value ICHR2 Reset Value ICLR2 Reset Value
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9.4 SERIAL PERIPHERAL INTERFACE (SPI) 9.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 9.4.2 Main Features s Full duplex synchronous transfers (on 3 lines) s Simplex synchronous transfers (on 2 lines) s Master or slave operation s Six master mode frequencies (fCPU/4 max.) s fCPU/2 max. slave mode frequency (see note) s SS Management by software or hardware s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 9.4.3 General Description Figure 53 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through 4 pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master Device.
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Figure 53. Serial Peripheral Interface Block Diagram
Data/Address Bus SPIDR Read Read Buffer Interrupt request
MOSI MISO
7
8-Bit Shift Register
SPIF WCOL OVR MODF 0
SPICSR
SOD SSM
0 SSI
SOD bit
Write
SS
SPI STATE CONTROL
7 SPIE
1 0
SCK
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 54. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device reFigure 54. Single Master/ Single Slave Application
sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 57) but master and slave must be programmed with the same timing mode.
MASTER MSBit LSBit MISO MISO MSBit
SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK SS +5V
SCK SS
Not used if SS is managed by software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 56) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: - SS internal must be held high continuously
In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 55): If CPHA=1 (data latched on 2nd clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): - SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 9.4.5.3).
Figure 55. Generic SS Timing Diagram
MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1)
Byte 1
Byte 2
Byte 3
Figure 56. Hardware/Software Slave Select Management SSM bit
SSI bit SS external pin
1 0
SS internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account): 1. Write to the SPICR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 57 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: - Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: - Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). The transmit sequence begins when software writes a byte in the SPIDR register. 9.4.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 9.4.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 57). Note: The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Section 9.4.3.2 and Figure 55. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 9.4.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 9.4.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 57). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 57. Data Clock Timing Diagram
Figure 57, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
CPHA =1
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.5 Error Flags 9.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the Device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the Device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device, the MODF bit can not be set, but in a multi master configuration the Device can be in slave mode with the MODF bit set. The MODF bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state.
9.4.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: - The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 9.4.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 9.4.3.2 Slave Select Management. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the CPU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 58).
Figure 58. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0 WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR
RESULT
Read SPIDR
WCOL=0
Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.5.4 Single Master and Multimaster Configurations There are two types of SPI systems: - Single Master System - Multimaster System Single Master System A typical single master system may be configured, using a device as the master and four devices as slaves (see Figure 59). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.
For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields. Multi-Master System A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.
Figure 59. Single Master / Multiple Slave Configuration
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
SS SCK Slave Device MOSI MISO
MOSI MISO SCK Master Device 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.6 Low Power Modes
Mode WAIT Description No effect on SPI. SPI interrupt events cause the Device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up by an interrupt with "exit from HALT mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.
SS pin or the SSI bit in the SPICSR register) is low when the Device enters Halt mode. So if Slave selection is configured as external (see Section 9.4.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 9.4.7 Interrupts
Interrupt Event Event Flag Enable Control Bit Exit from Wait Yes SPIE Yes Yes Exit from Halt Yes No No
HALT
SPI End of TransSPIF fer Event Master Mode MODF Fault Event Overrun Error OVR
9.4.6.1 Using the SPI to wake-up the Device from Halt mode In slave configuration, the SPI is able to wake-up the Device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake-up the Device from Halt mode only if the Slave Select signal (external
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 9.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh)
7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 0 SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register) Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 9.4.5.1 Master Mode Fault (MODF)). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 18 SPI Master mode SCK Frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 9.4.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 18. SPI Master mode SCK Frequency Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)
7 SPIF WCOL OVR MODF SOD SSM 0 SSI
Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 9.4.3.2 Slave Select Management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the Device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 58). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 9.4.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 9.4.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared.
The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 53).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 19. SPI Register Map and Reset Values
Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPICSR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x SSI 0
x SPE 0 WCOL 0
x SPR2 0 OR 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x SOD 0
x SPR1 x SSM 0
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9.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) 9.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. The LIN-dedicated features support the LIN (Local Interconnect Network) protocol for both master and slave nodes. This chapter is divided into SCI Mode and LIN mode sections. For information on general SCI communications, refer to the SCI mode section. For LIN applications, refer to both the SCI mode and LIN mode sections. 9.5.2 SCI Features s Full duplex, asynchronous communications s NRZ standard format (Mark/Space) s Independently programmable transmit and receive baud rates up to 500K baud. s Programmable data word length (8 or 9 bits) s Receive buffer full, Transmit buffer empty and End of Transmission flags s Two receiver wake-up modes: - Address bit (MSB) - Idle line s Muting function for multiprocessor configurations s Separate enable bits for Transmitter and Receiver s Overrun, Noise and Frame error detection Six interrupt sources - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error - Parity interrupt s Parity control: - Transmits parity bit - Checks parity of received data byte s Reduced power consumption mode 9.5.3 LIN Features - LIN Master - 13-bit LIN Synch Break generation - LIN Slave - Automatic Header Handling - Automatic baud rate re-synchronization based on recognition and measurement of the LIN Synch Field (for LIN slave nodes) - Automatic baud rate adjustment (at CPU frequency precision) - 11-bit LIN Synch Break detection capability - LIN Parity check on the LIN Identifier Field (only in reception) - LIN Error management - LIN Header Timeout - Hot plugging support
s
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LINSCI SERIAL COMMUNICATION INTERFACE (Cont'd) 9.5.4 General Description - A conventional type for commonly-used baud rates. The interface is externally connected to another device by two pins: - An extended type with a prescaler offering a very wide range of baud rates even with non-standard - TDO: Transmit Data Output. When the transmitoscillator frequencies. ter is disabled, the output pin returns to its I/O port configuration. When the transmitter is ena- A LIN baud rate generator with automatic resynbled and nothing is to be transmitted, the TDO chronization. pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through these pins, serial data is transmitted and received as characters comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the character is complete. This interface uses three types of baud rate generator:
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LINSCI
SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd)
Figure 60. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
Write
Read
(DATA REGISTER) SCIDR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Receive Shift Register
SCICR1
R8 T8 SCID M
WAKE PCE
PS PIE
TRANSMIT CONTROL
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
SCICR2
TIE TCIE RIE ILIE TE RE RWU SBK OR/ TDRE TC RDRF IDLE LHE NF FE
SCISR
PE
SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE
fCPU
CONTROL
/16
/PR SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.5 SCI Mode - Functional Description 9.5.5.1 Serial Data Format Conventional Baud Rate Generator Mode Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 regThe block diagram of the Serial Control Interface ister (see Figure 61). in conventional baud rate generator mode is shown in Figure 60. The TDO pin is in low state during the start bit. It uses 4 registers: The TDO pin is in high state during the stop bit. - Two control registers (SCICR1 and SCICR2) An Idle character is interpreted as a continuous logic high level for 10 (or 11) full bit times. - A status register (SCISR) A Break character is a character with a sufficient - A baud rate register (SCIBRR) number of low level bits to break the normal data Extended Prescaler Mode format followed by an extra "1" bit to acknowledge the start bit. Two additional prescalers are available in extended prescaler mode. They are shown in Figure 62. - An extended prescaler receiver register (SCIERPR) - An extended prescaler transmitter register (SCIETPR)
Figure 61. Word length programming 9-bit Word length (M bit is set) Data Character
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8
Next Data Character
Next Stop Start Bit Bit Start Bit
Idle Line
Break Character
Extra '1'
Start Bit
8-bit Word length (M bit is reset) Data Character
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Character
Next Start Bit Start Bit Extra Start Bit '1'
Idle Line Break Character
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.5.2 Transmitter When no transmission is taking place, a write instruction to the SCIDR register places the data diThe transmitter can send data words of either 8 or rectly in the shift register, the data transmission 9 bits depending on the M bit status. When the M starts, and the TDRE bit is immediately set. bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 When a character transmission is complete (after register. the stop bit or after the break character) the TC bit is set and an interrupt is generated if the TCIE is Character Transmission set and the I[1:0] bits are cleared in the CCR regDuring an SCI transmission, data shifts out least ister. significant bit first on the TDO pin. In this mode, Clearing the TC bit is performed by the following the SCIDR register consists of a buffer (TDR) besoftware sequence: tween the internal bus and the transmit shift regis1. An access to the SCISR register ter (see Figure 60). 2. A write to the SCIDR register Procedure Note: The TDRE and TC bits are cleared by the - Select the M bit to define the word length. same software sequence. - Select the desired baud rate using the SCIBRR Break Characters and the SCIETPR registers. Setting the SBK bit loads the shift register with a - Set the TE bit to send a preamble of 10 (M=0) or break character. The break character length de11 (M=1) consecutive ones (Idle Line) as first pends on the M bit (see Figure 61) transmission. As long as the SBK bit is set, the SCI sends break - Access the SCISR register and write the data to characters to the TDO pin. After clearing this bit by send in the SCIDR register (this sequence clears software, the SCI inserts a logic 1 bit at the end of the TDRE bit). Repeat this sequence for each the last break character to guarantee the recognidata to be transmitted. tion of the start bit of the next character. Clearing the TDRE bit is always performed by the Idle Line following software sequence: Setting the TE bit drives the SCI to send a pream1. An access to the SCISR register ble of 10 (M=0) or 11 (M=1) consecutive `1's (idle 2. A write to the SCIDR register line) before the first character. The TDRE bit is set by hardware and it indicates: In this case, clearing and then setting the TE bit - The TDR register is empty. during a transmission sends a preamble (idle line) after the current word. Note that the preamble du- The data transfer is beginning. ration (10 or 11 consecutive `1's depending on the - The next data can be written in the SCIDR regisM bit) does not take into account the stop bit of the ter without overwriting the previous data. previous character. This flag generates an interrupt if the TIE bit is set Note: Resetting and setting the TE bit causes the and the I[|1:0] bits are cleared in the CCR register. data in the TDR register to be lost. Therefore the When a transmission is taking place, a write inbest time to toggle the TE bit is when the TDRE bit struction to the SCIDR register stores the data in is set i.e. before writing the next byte in the SCIDR. the TDR register and which is copied in the shift register at the end of the current transmission.
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.5.3 Receiver - The OR bit is set. The SCI can receive data words of either 8 or 9 - The RDR content will not be lost. bits. When the M bit is set, word length is 9 bits - The shift register will be overwritten. and the MSB is stored in the R8 bit in the SCICR1 - An interrupt is generated if the RIE bit is set and register. the I[|1:0] bits are cleared in the CCR register. Character reception The OR bit is reset by an access to the SCISR regDuring a SCI reception, data shifts in least signifiister followed by a SCIDR register read operation. cant bit first through the RDI pin. In this mode, the Noise Error SCIDR register consists or a buffer (RDR) between the internal bus and the received shift regisOversampling techniques are used for data recovter (see Figure 60). ery by discriminating between valid incoming data and noise. Procedure When noise is detected in a character: - Select the M bit to define the word length. - The NF bit is set at the rising edge of the RDRF - Select the desired baud rate using the SCIBRR bit. and the SCIERPR registers. - Data is transferred from the Shift register to the - Set the RE bit, this enables the receiver which SCIDR register. begins searching for a start bit. - No interrupt is generated. However this bit rises When a character is received: at the same time as the RDRF bit which itself - The RDRF bit is set. It indicates that the content generates an interrupt. of the shift register is transferred to the RDR. The NF bit is reset by a SCISR register read oper- An interrupt is generated if the RIE bit is set and ation followed by a SCIDR register read operation. the I[1:0] bits are cleared in the CCR register. Framing Error - The error flags can be set if a frame error, noise A framing error is detected when: or an overrun error has been detected during reception. - The stop bit is not recognized on reception at the expected time, following either a de-synchroniClearing the RDRF bit is performed by the following zation or excessive noise. software sequence done by: - A break is received. 1. An access to the SCISR register When the framing error is detected: 2. A read to the SCIDR register. - the FE bit is set by hardware The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun - Data is transferred from the Shift register to the error. SCIDR register. Idle Line - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself When an idle line is detected, there is the same generates an interrupt. procedure as a data received character plus an interrupt if the ILIE bit is set and the I[|1:0] bits are The FE bit is reset by a SCISR register read opercleared in the CCR register. ation followed by a SCIDR register read operation. Overrun Error Break Character An overrun error occurs when a character is re- When a break character is received, the SCI ceived when RDRF has not been reset. Data can handles it as a framing error. To differentiate a not be transferred from the shift register to the break character from a framing error, it is necesTDR register as long as the RDRF bit is not sary to read the SCIDR. If the received value is cleared. 00h, it is a break character. Otherwise it is a framing error. When an overrun error occurs:
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.5.4 Conventional Baud Rate Generation 9.5.5.5 Extended Baud Rate Generation The baud rate for the receiver and transmitter (Rx The extended prescaler option gives a very fine and Tx) are set independently and calculated as tuning on the baud rate, using a 255 value prescalfollows: er, whereas the conventional Baud Rate Generator retains industry standard software compatibilifCPU fCPU ty. Rx = Tx = The extended baud rate generator block diagram (16*PR)*RR (16*PR)*TR is described in Figure 62. with: The output clock rate sent to the transmitter or to PR = 1, 3, 4 or 13 (see SCP[1:0] bits) the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the TR = 1, 2, 4, 8, 16, 32, 64,128 SCIERPR or the SCIETPR register. (see SCT[2:0] bits) Note: the extended prescaler is activated by setRR = 1, 2, 4, 8, 16, 32, 64,128 ting the SCIETPR or SCIERPR register to a value (see SCR[2:0] bits) other than zero. The baud rates are calculated as follows: All these bits are in the SCIBRR register. Example: If fCPU is 8 MHz (normal mode) and if fCPU fCPU PR=13 and TR=RR=1, the transmit and receive Rx = Tx = baud rates are 38400 baud. 16*ERPR*(PR*TR) 16*ETPR*(PR*TR) Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is enwith: abled. ETPR = 1,..,255 (see SCIETPR register) ERPR = 1,.. 255 (see SCIERPR register)
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LINSCI
SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd)
Figure 62. SCI Baud Rate and Extended Prescaler Block Diagram
TRANSMITTER CLOCK EXTENDED PRESCALER TRANSMITTER RATE CONTROL
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER RECEIVER CLOCK EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER
fCPU
TRANSMITTER RATE CONTROL
/16
/PR SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.5.6 Receiver Muting and Wake-up Feature ceived an address character (most significant bit ='1'), the receivers are waken up. The receivers In multiprocessor configurations it is often desirawhich are not addressed set RWU bit to enter in ble that only the intended message recipient mute mode. Consequently, they will not treat the should actively receive the full message contents, next characters constituting the next part of the thus reducing redundant SCI service overhead for message. all non-addressed receivers. 9.5.5.7 Parity Control The non-addressed devices may be placed in sleep mode by means of the muting function. Hardware byte Parity control (generation of parity bit in transmission and parity checking in recepSetting the RWU bit by software puts the SCI in tion) can be enabled by setting the PCE bit in the sleep mode: SCICR1 register. Depending on the character forAll the reception status bits can not be set. mat defined by the M bit, the possible SCI character formats are as listed in Table 20. All the receive interrupts are inhibited. Note: In case of wake up by an address mark, the A muted receiver may be woken up in one of the MSB bit of the data is taken into account and not following ways: the parity bit - by Idle Line detection if the WAKE bit is reset, - by Address Mark detection if the WAKE bit is set. Table 20. Character Formats Idle Line Detection M bit PCE bit Character format 0 0 | SB | 8 bit data | STB | Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Line. Then 0 1 | SB | 7-bit data | PB | STB | the RWU bit is reset by hardware but the IDLE bit 1 0 | SB | 9-bit data | STB | is not set. 1 1 | SB | 8-bit data | PB | STB | This feature is useful in a multiprocessor system Legend: SB = Start Bit, STB = Stop Bit, when the first characters of the message deterPB = Parity Bit mine the address and when each message ends Even parity: the parity bit is calculated to obtain by an idle line: As soon as the line becomes idle, an even number of "1s" inside the character made every receivers is waken up and analyse the first of the 7 or 8 LSB bits (depending on whether M is characters of the message which indicates the adequal to 0 or 1) and the parity bit. dressed receiver. The receivers which are not addressed set RWU bit to enter in mute mode. ConEx: data=00110101; 4 bits set => parity bit will be sequently, they will not treat the next characters 0 if even parity is selected (PS bit = 0). constituting the next part of the message. At the Odd parity: the parity bit is calculated to obtain an end of the message, an idle line is sent by the odd number of "1s" inside the character made of transmitter: this wakes up every receivers which the 7 or 8 LSB bits (depending on whether M is are ready to analyse the addressing characters of equal to 0 or 1) and the parity bit. the new message. Ex: data=00110101; 4 bits set => parity bit will be In such a system, the inter-characters space must 1 if odd parity is selected (PS bit = 1). be smaller than the idle time. Transmission mode: If the PCE bit is set then the Address Mark Detection MSB bit of the data written in the data register is Receiver wakes-up by Address Mark detection not transmitted but is changed by the parity bit. when it received a "1" as the most significant bit of Reception mode: If the PCE bit is set then the ina word, thus indicating that the message is an adterface checks if the received data byte has an dress. The reception of this particular word wakes even number of "1s" if even parity is selected up the receiver, resets the RWU bit and sets the (PS=0) or an odd number of "1s" if odd parity is seRDRF bit, which allows the receiver to receive this lected (PS=1). If the parity check fails, the PE flag word normally and to use it as an address word. is set in the SCISR register and an interrupt is genThis feature is useful in a multiprocessor system erated if PCIE is set in the SCICR1 register. when the most significant bit of each character (except for the break character) is reserved for Address Detection. As soon as the receivers re-
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.6 Low Power Modes 9.5.7 Interrupts
Mode WAIT
Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Interrupt Event
Enable Exit Event Control from Flag Bit Wait TIE TCIE Yes Yes Yes RIE Yes ILIE PIE LHIE Yes Yes Yes
Exit from Halt No No No No No No No
HALT
Transmit Data Register TDRE Empty Transmission ComTC plete Received Data Ready RDRF to be Read Overrun Error or LIN OR/ Synch Error Detected LHE Idle Line Detected IDLE Parity Error PE LIN Header Detection LHDF
The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) 9.5.8 SCI Mode Register Description Bit 3 = OR Overrun error STATUS REGISTER (SCISR) The OR bit is set by hardware when the word curRead Only rently being received in the shift register is ready to Reset Value: 1100 0000 (C0h) be transferred into the RDR register whereas RDRF is still set. An interrupt is generated if RIE=1 7 0 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register folTDRE TC RDRF IDLE OR1) NF1) FE1) PE1) lowed by a read to the SCIDR register). 0: No Overrun error 1: Overrun error detected Bit 7 = TDRE Transmit data register empty. Note: When this bit is set, RDR register contents This bit is set by hardware when the content of the TDR register has been transferred into the shift will not be lost but the shift register will be overwritten. register. An interrupt is generated if the TIE =1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed Bit 2 = NF Character Noise flag by a write to the SCIDR register). 0: Data is not transferred to the shift register This bit is set by hardware when noise is detected 1: Data is transferred to the shift register on a received character. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). Bit 6 = TC Transmission complete. 0: No noise This bit is set by hardware when transmission of a 1: Noise is detected character containing Data is complete. An interNote: This bit does not generate interrupt as it aprupt is generated if TCIE=1 in the SCICR2 regispears at the same time as the RDRF bit which itter. It is cleared by a software sequence (an acself generates an interrupt. cess to the SCISR register followed by a write to the SCIDR register). 0: Transmission is not complete Bit 1 = FE Framing error. 1: Transmission is complete This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break. tected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). Bit 5 = RDRF Received data ready flag. 0: No Framing error This bit is set by hardware when the content of the 1: Framing error or break character detected RDR register has been transferred to the SCIDR Notes: register. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software se- This bit does not generate an interrupt as it apquence (an access to the SCISR register followed pears at the same time as the RDRF bit which itby a read to the SCIDR register). self generates an interrupt. If the word currently 0: Data is not received being transferred causes both a frame error and 1: Received data is ready to be read an overrun error, it will be transferred and only the OR bit will be set. Bit 4 = IDLE Idle line detected. Bit 0 = PE Parity error. This bit is set by hardware when an Idle Line is deThis bit is set by hardware when a byte parity error tected. An interrupt is generated if the ILIE=1 in occurs (if the PCE bit is set) in receiver mode. It is the SCICR2 register. It is cleared by a software secleared by a software sequence (a read to the staquence (an access to the SCISR register followed tus register followed by an access to the SCIDR by a read to the SCIDR register). data register). An interrupt is generated if PIE=1 in 0: No Idle Line is detected the SCICR1 register. 1: Idle Line is detected 0: No parity error 1: Parity error detected Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs).
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) CONTROL REGISTER 1 (SCICR1) Read/Write Bit 3 = WAKE Wake-Up method. Reset Value: x000 0000 (x0h) This bit determines the SCI Wake-Up method, it is set or cleared by software. 7 0 0: Idle Line 1: Address Mark 1) R8 T8 SCID M WAKE PCE PS PIE Note: If the LINE bit is set, the WAKE bit is de-activated and replaced by the LHDM bit
1)This
bit has a different function in LIN mode, please refer to the LIN mode register description.
Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Note: The M bit must not be modified during a data transfer (both transmission and reception).
Bit 2 = PCE Parity control enable. This bit is set and cleared by software. It selects the hardware parity control (generation and detection for byte parity, detection only for LIN parity). 0: Parity control disabled 1: Parity control enabled Bit 1 = PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). The parity error involved can be a byte parity error (if bit PCE is set and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is set). 0: Parity error interrupt disabled 1: Parity error interrupt enabled
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) CONTROL REGISTER 2 (SCICR2) 1: Receiver is enabled and begins searching for a Read/Write start bit Reset Value: 0000 0000 (00 h) Bit 1 = RWU Receiver wake-up. 7 0 This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be 1) SBK1) TIE TCIE RIE ILIE TE RE RWU cleared by hardware when a wake-up sequence is recognized. 1)This bit has a different function in LIN mode, please 0: Receiver in active mode 1: Receiver in mute mode refer to the LIN mode register description. Notes: Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. - Before selecting Mute mode (by setting the RWU 0: Interrupt is inhibited bit) the SCI must first receive a data byte, other1: In SCI interrupt is generated whenever TDRE=1 wise it cannot function in Mute mode with wakein the SCISR register up by Idle line detection. - In Address Mark Detection Wake-Up configuraBit 6 = TCIE Transmission complete interrupt enation (WAKE bit=1) the RWU bit cannot be modible fied by software while the RDRF bit is set. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 0 = SBK Send break. 1: An SCI interrupt is generated whenever TC=1 in This bit set is used to send break characters. It is the SCISR register set and cleared by software. 0: No break character is transmitted Bit 5 = RIE Receiver interrupt enable. 1: Break characters are transmitted This bit is set and cleared by software. Note: If the SBK bit is set to "1" and then to "0", the 0: Interrupt is inhibited transmitter will send a BREAK word at the end of 1: An SCI interrupt is generated whenever OR=1 the current word. or RDRF=1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Notes: - During transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble (idle line) after the current word. - When TE is set there is a 1 bit-time delay before the transmission starts. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled in the SCISR register
DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
DR7 DR6 DR5 DR4 DR3 DR2 DR1
0
DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 60). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 60).
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) BAUD RATE REGISTER (SCIBRR) TR dividing factor Read/Write 1 Reset Value: 0000 0000 (00h)
SCT2 0 0 0 0 1 1 1 1
SCT1 0 0 1 1 0 0 1 1
SCT0 0 1 0 1 0 1 0 1
2 7
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2
0
SCR1 SCR0
4 8 16 32 64 128
Note: When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate generator. Bit 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1
Bit 2:0 = SCR[2:0] SCI Receiver rate divider. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
RR dividing factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
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LINSCI SERIAL COMMUNICATION INTERFACE (SCI Mode) (Cont'd) EXTENDED RECEIVE PRESCALER DIVISION EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIERPR) REGISTER (SCIETPR) Read/Write Read/Write Reset Value: 0000 0000 (00 h) Reset Value:0000 0000 (00h)
7
0
7
ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2
0
ETPR ETPR 1 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0
Bit 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see Figure 62) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not active after a reset.
Bit 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value other than 00h is stored in this register. The clock frequency from the 16 divider (see Figure 62) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not active after a reset. Note: In LIN slave mode, the Conventional and Extended Baud Rate Generators are disabled.
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) 9.5.9 LIN Mode - Functional Description. Slave The block diagram of the Serial Control Interface, Set the LSLV bit in the SCICR3 register to enter in LIN slave mode is shown in Figure 64. LIN slave mode. In this case, setting the SBK bit will have no effect. It uses 6 registers: In LIN Slave mode the LIN baud rate generator is - Three control registers: SCICR1, SCICR2 and selected instead of the Conventional or Extended SCICR3 Prescaler. The LIN baud rate generator is com- Two status registers: the SCISR register and the mon to the transmitter and the receiver. LHLR register mapped at the SCIERPR address Then the baud rate can be programmed using - A baud rate register: LPR mapped at the SCILPR and LPRF registers. BRR address and an associated fraction register Note: It is mandatory to set the LIN configuration LPFR mapped at the SCIETPR address first before programming LPR and LPRF, because The bits dedicated to LIN are located in the the LIN configuration uses a different baud rate SCICR3. Refer to the register descriptions in Secgenerator from the standard one. tion 9.5.10for the definitions of each bit. 9.5.9.1 Entering LIN Mode 9.5.9.2 LIN Transmission To use the LINSCI in LIN mode the following conIn LIN mode the same procedure as in SCI mode figuration must be set in SCICR3 register: has to be applied for a LIN transmission. - Clear the M bit to configure 8-bit word length. To transmit the LIN Header the proceed as fol- Set the LINE bit. lows: Master - First set the SBK bit in the SCICR2 register to start transmitting a 13-bit LIN Synch Break To enter master mode the LSLV bit must be reset In this case, setting the SBK bit will send 13 low - reset the SBK bit bits. - Load the LIN Synch Field (0x55) in the SCIDR Then the baud rate can programmed using the register to request Synch Field transmission SCIBRR, SCIERPR and SCIETPR registers. - Wait until the SCIDR is empty (TDRE bit set in In LIN master mode, the Conventional and / or Exthe SCISR register) tended Prescaler define the baud rate (as in stand- Load the LIN message Identifier in the SCIDR ard SCI mode) register to request Identifier transmission.
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Figure 63. LIN characters 8-bit Word length (M bit is reset) Next Data Character Next Start Start Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop Bit Bit Bit0 Bit1 Bit Idle Line LIN Synch Break = 13 low bits Start Bit LIN Synch Field Extra Start '1' Bit Data Character
LIN Synch Field Next Start Stop Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit Bit Measurement for baud rate autosynchronization
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LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd)
Figure 64. SCI Block Diagram in LIN Slave Mode
Write
Read
(DATA REGISTER) SCIDR
Transmit Data Register (TDR)
Received Data Register (RDR)
TDO
Transmit Shift Register
Receive Shift Register
RDI
SCICR1
R8 T8 SCID M
WAKE PCE
PS PIE
TRANSMIT CONTROL
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
SCICR2
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR/ LHE NF FE
SCISR
PE
SCI INTERRUPT CONTROL TRANSMITTER CLOCK
fCPU
LIN SLAVE BAUD RATE AUTO SYNCHRONIZATION UNIT
SCICR3
LDUM LINE LSLV LASE LHDM LHIE LHDF LSF
SCIBRR
LPR7 LPR0 CONVENTIONAL BAUD RATE GENERATOR + EXTENDED PRESCALER 0
fCPU
/ LDIV
/16
1
LIN SLAVE BAUD RATE GENERATOR
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) 9.5.9.3 LIN Reception Note: In LIN mode the reception of a byte is the same as In LIN slave mode, the FE bit detects all frame erin SCI mode but the LINSCI has features for hanror which does not correspond to a break. dling the LIN Header automatically (identifier deIdentifier Detection (LHDM = 1): tection) or semiautomatically (Synch Break detecThis case is the same as the previous one except tion) depending on the LIN Header detection that the LHDF and the RDRF flags are set only afmode. The detection mode is selected by the ter the entire header has been received (this is LHDM bit in the SCICR3. true whether automatic resynchronization is enaAdditionally, an automatic resynchronization feabled or not). This indicates that the LIN Identifier is ture can be activated to compensate for any clock available in the SCIDR register. deviation, for more details please refer to Section Notes: 9.5.9.5 LIN Baudrate. During LIN Synch Field measurement, the SCI LIN Header Handling by a Slave state machine is switched off: no characters are Depending on the LIN Header detection method transferred to the data register. the LINSCI will signal the detection of a LIN HeadLIN Slave parity er after the LIN Synch Break or after the Identifier has been successfully received. In LIN Slave mode (LINE and LSLV bits are set) LIN parity checking can be enabled by setting the Note: PCE bit. It is recommended to combine the Header detecIn this case, the parity bits of the LIN Identifier tion function with Mute mode. Putting the LINSCI Field are checked. The identifier character is recin Mute mode allows the detection of Headers only ognised as the 3rd received character after a break and prevents the reception of any other characcharacter (included): ters. This mode can be used to wait for the next Header parity bits without being interrupted by the data bytes of the current message in case this message is not relevant for the application. Synch Break Detection (LHDM = 0): When a LIN Synch Break is received: LIN Synch LIN Synch Identifier Field Break Field - The RDRF bit in the SCISR register is set. It indicates that the content of the shift register is transferred to the SCIDR register, a value of 0x00 is expected for a Break. The bits involved are the two MSB positions (7th and 8th bits if M=0; 8th and 9th bits if M=0) of the - The LHDF flag in the SCICR3 register indicates identifier character. The check is performed as that a LIN Synch Break Field has been detected. specified by the LIN specification: - An interrupt is generated if the LHIE bit in the SCICR3 register is set and the I[1:0] bits are cleared in the CCR register. parity bits stop bit start bit - Then the LIN Synch Field is received and measidentifier bits ured. ID0 ID1 ID2 ID3 ID4 ID5 P0 P1 - If automatic resynchronization is enabled (LASE bit = 1), the LIN Synch Field is not transIdentifier Field ferred to the shift register: there is no need to clear the RDRF bit. P0 = ID0 ID1 ID2 ID4 M=0 - If automatic resynchronization is disabled (LAP1 = ID1 ID3 ID4 ID5 SE bit =0), the LIN Synch Field is received as a normal character and transferred to the SCIDR register and RDRF is set.
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) 9.5.9.4 LIN Error Detection edge of the Synch Field. Let's refer to this period deviation as D: LIN Header Error Flag If the LHE flag is set, it means that: The LIN Header Error Flag indicates that an invalid LIN Header has been detected. D > 15.625% When a LIN Header Error occurs: If LHE flag is not set, it means that: - The LHE flag is set D < 16.40625% - An interrupt is generated if the RIE bit is set and If 15.625% D < 16.40625%, then the flag can the I[1:0] bits are cleared in the CCR register. be either set or reset depending on the dephasing between the signal on the RDI line and the If autosynchronization is enabled (LASE bit =1), CPU clock. this can mean that the LIN Synch Field is corrupted, and that the SCI is in a blocked state (LSF bit is - The second check is based on the measurement set). The only way to recover is to reset the LSF bit of each bit time between both edges of the Synch and then to clear the LHE bit. Field: this checks that each of these bit times is large enough compared to the bit time of the cur- The LHE bit is reset by an access to the SCISR rent baud rate. register followed by a read of the SCIDR register. When LHE is set due to this error then the SCI LHE/OVR Error Conditions goes into a blocked state (LSF bit is set). When Auto Resynchronization is disabled (LASE LIN Header Time-out Error bit =0), the LHE flag detects: When the LIN Identifier Field Detection Method is - That the received LIN Synch Field is not equal to used (by configuring LHDM to 1) or when LIN 55h. auto-resynchronization is enabled (LASE bit=1), - That an overrun occurred (as in standard SCI the LINSCI automatically monitors the mode) THEADER_MAX condition given by the LIN protocol. - Furthermore, if LHDM is set it also detects that a If the entire Header (up to and including the STOP LIN Header Reception Timeout occurred (only if bit of the LIN Identifier Field) is not received within LHDM is set). the maximum time limit of 57 bit times then a LIN Header Error is signalled and the LHE bit is set in When the LIN auto-resynchronization is enabled the SCISR register. (LASE bit=1), the LHE flag detects: - That the deviation error on the Synch Field is Figure 65. LIN Header Reception Timeout outside the LIN specification which allows up to +/-15.5% of period deviation between the slave and master oscillators. LIN Synch LIN Synch Identifier - A LIN Header Reception Timeout occurred. Field Break Field If THEADER > THEADER_MAX then the LHE flag is set. Refer to Figure 65. (only if LHDM is set to 1) THEADER - An overflow during the Synch Field Measurement, which leads to an overflow of the divider registers. If LHE is set due to this error then the The time-out counter is enabled at each break deSCI goes into a blocked state (LSF bit is set). tection. It is stopped in the following conditions: - That an overrun occurred on Fields other than - A LIN Identifier Field has been received the Synch Field (as in standard SCI mode) - An LHE error occurred (other than a timeout erDeviation Error on the Synch Field ror). - A software reset of LSF bit (transition from high to The deviation error is checking by comparing the low) occurred during the analysis of the LIN Synch current baud rate (relative to the slave oscillator) Field or with the received LIN Synch Field (relative to the master oscillator). Two checks are performed in If LHE bit is set due to this error during the LIN parallel: Synchr Field (if LASE bit = 1) then the SCI goes into a blocked state (LSF bit is set). - The first check is based on a measurement between the first falling edge and the last falling
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) If LHE bit is set due to this error during Fields other Even if no timeout occurs on the LIN Header, it is than LIN Synch Field or if LASE bit is reset then possible to have access to the effective LIN headthe current received Header is discarded and the er Length (THEADER) through the LHL register. This allows monitoring at software level the SCI searches for a new Break Field. TFRAME_MAX condition given by the LIN protocol. Note on LIN Header Time-out Limit This feature is only available when LHDM bit =1 or According to the LIN specification, the maximum when LASE bit =1. length of a LIN Header which does not cause a Mute Mode and Errors timeout is equal to 1.4*(34 + 1) = 49 TBIT_MASTER. TBIT_MASTER refers to the master baud rate. In mute mode when LHDM bit =1, if an LHE error occurs during the analysis of the LIN Synch Field When checking this timeout, the slave node is deor if a LIN Header Time-out occurs then the LHE synchronized for the reception of the LIN Break bit is set but it doesn't wake up from mute mode. In and Synch fields. Consequently, a margin must be this case, the current header analysis is discarded. allowed, taking into account the worst case: this If needed, the software has to reset LSF bit. Then occurs when the LIN identifier lasts exactly 10 the SCI searches for a new LIN header. TBIT_MASTER periods. In this case, the LIN Break and Synch fields last 49-10 = 39TBIT_MASTER periIn mute mode, if a framing error occurs on a data ods. (which is not a break), it is discarded and the FE bit is not set. Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This leads When LHDM bit =1, any LIN header which reto a maximum allowed Header Length of: spects the following conditions causes a wake up from mute mode: 39 x (1/0.845) TBIT_MASTER + 10TBIT_MASTER - A valid LIN Break Field (at least 11 dominant bits = 56.15 TBIT_SLAVE followed by a recessive bit) A margin is provided so that the time-out occurs - A valid LIN Synch Field (without deviation error) when the header length is greater than 57 TBIT_SLAVE periods. If it is less than or equal to 57 - A LIN Identifier Field without framing error. Note TBIT_SLAVE periods, then no timeout occurs. that a LIN parity error on the LIN Identifier Field does not prevent wake up from mute mode. LIN Header Length - No LIN Header Time-out should occur during Header reception.
Figure 66. LIN Synch Field Measurement tCPU = CPU period tBR = 16.LP.tCPU tBR = Baud Rate period SM=Synch Measurement Register (15 bits) tBR LIN Synch Field Next LIN Synch Break Start Extra Stop Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit Bit '1' Measurement = 8.TBR = SM.tCPU LPR(n) LPR = tBR / (16.tCPU) = Rounding (SM / 128) LPR(n+1)
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) 9.5.9.5 LIN Baudrate mitter are both set to the same value, depending on the LIN Slave baud rate generator: Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. fCPU Automatic Resynchronization Tx = Rx = (16*LDIV) To automatically adjust the baud rate based on measurement of the LIN Synch Field: with: - Write the nominal LIN Prescaler value (usually LDIV is an unsigned fixed point number. The mandepending on the nominal baud rate) in the tissa is coded on 8 bits in the LPR register and the LPFR / LPR registers. fraction is coded on 4 bits in the LPFR register. - Set the LASE bit to enable the Auto SynchroniIf LASE bit = 1 then LDIV is automatically updated zation Unit. at the end of each LIN Synch Field. When Auto Synchronization is enabled, after each Three registers are used internally to manage the LIN Synch Break, the time duration between 5 fallauto-update of the LIN divider (LDIV): ing edges on RDI is sampled on fCPU and the re- LDIV_NOM (nominal value written by software at sult of this measurement is stored in an internal LPR/LPFR addresses) 15-bit register called SM (not user accessible) (See Figure 66). Then the LDIV value (and its as- LDIV_MEAS (results of the Field Synch meassociated LPFR and LPR registers) are automatiurement) cally updated at the end of the fifth falling edge. - LDIV (used to generate the local baud rate) During LIN Synch field measurement, the SCI The control and interactions of these registers is state machine is stopped and no data is transexplained in Figure 67 and Figure 68. It depends ferred to the data register. on the LDUM bit setting (LIN Divider Update Meth9.5.9.6 LIN Slave Baud Rate Generation od) In LIN mode, transmission and reception are drivNote: en by the LIN baud rate generator As explained in Figure 67 and Figure 68, LDIV Note: LIN Master mode uses the Extended or can be updated by two concurrent actions: a Conventional prescaler register to generate the transfer from LDIV_MEAS at the end of the LIN baud rate. Sync Field and a transfer from LDIV_NOM due If LINE bit = 1 and LSLV bit = 1 then the Convento a software write of LPR. If both operations tional and Extended Baud Rate Generators are occur at the same time, the transfer from disabled: the baud rate for the receiver and transLDIV_NOM has priority.
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LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd)
Figure 67. LDIV Read / Write operations when LDUM=0 Write LPR Write LPFR LIN Sync Field Measurement
MANT(7:0) FRAC(3:0)
LDIV_NOM
Write LPR MANT(7:0) FRAC(3:0) LDIV_MEAS Update at end of Synch Field
MANT(7:0) FRAC(3:0) LDIV
Baud Rate Generarion
Read LPR
Read LPFR
Figure 68. LDIV Read / Write operations when LDUM=1 Write LPR Write LPFR LIN Sync Field Measurement
MANT(7:0) FRAC(3:0)
LDIV_NOM
RDRF=1 MANT(7:0) FRAC(3:0) LDIV_MEAS Update at end of Synch Field
MANT(7:0) FRAC(3:0) LDIV
Baud Rate Generarion
Read LPR
Read LPFR
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) 9.5.9.7 LINSCI Clock Tolerance Consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit. LINSCI Clock Tolerance when unsynchronized The sampling clock is resynchronized at each start When LIN slaves are unsynchronized (meaning no bit, so that when receiving 10 bits (one start bit, 1 characters have been transmitted for a relatively data byte, 1 stop bit), the clock deviation should long time), the maximum tolerated deviation of the not exceed 3.75%. LINSCI clock is +/-15%. 9.5.9.8 Clock Deviation Causes If the deviation is within this range then the LIN Synch Break is detected properly when a new reThe causes which contribute to the total deviation ception occurs. are: This is made possible by the fact that masters - DTRA: Deviation due to transmitter error. Note: the transmitter can be either a master or send 13 low bits for the LIN Synch Break, which a slave (in case of a slave listening to the recan be interpreted as 11 low bits (13 bits -15% = sponse of another slave). 11.05) by a "fast" slave and then considered as a LIN Synch Break. According to the LIN specifica- DMEAS: Error due to the LIN Synch measuretion, a LIN Synch Break is valid when its duration ment performed by the receiver. is greater than tSBRKTS = 10. This means that the - DQUANT: Error due to the baud rate quantisaLIN Synch Break must last at least 11 low bits. tion of the receiver. Note: If the period desynchronization of the slave - DREC: Deviation of the local oscillator of the is +15% (slave too slow), the character "00h" receiver: This deviation can occur during the which represents a sequence of 9 low bits must reception of one complete LIN message asnot be interpreted as a break character (9 bits + suming that the deviation has been compen15% = 10.35). Consequently, a valid LIN Synch sated at the beginning of the message. break must last at least 11 low bits. - DTCL: Deviation due to the transmission line LINSCI Clock Tolerance when Synchronized (generally due to the transceivers) When synchronization has been performed, folAll the deviations of the system should be added lowing reception of a LIN Synch Break, the LINSCI, and compared to the LINSCI clock tolerance: in LIN mode, has the same clock deviation tolerDTRA + DMEAS +D QUANT + DREC + D TCL < 3.75% ance as in SCI mode, which is explained below: During reception, each bit is oversampled 16 times. The mean of the 8 th, 9thand 10th samples is considered as the bit value.
Figure 69. Bit Sampling in Reception Mode
RDI LINE sampled values Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
6/16 7/16 One bit time 7/16
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) 9.5.9.9 Error due to LIN Synch measurement Consequently, at a given CPU frequency, the maximum possible nominal baud rate (LPRMIN) The LIN Synch Field is measured over eight bit should be chosen with respect to the maximum toltimes. erated deviation given by the equation: This measurement is performed using a counter DTRA + 2 / (128*LDIVMIN) + 1 / (2*16*LDIVMIN) clocked by the CPU clock. The edge detections + DREC + DTCL < 3.75% are performed using the CPU clock cycle. This leads to a precision of 2 CPU clock cycles for the measurement which lasts 16*8*LDIV clock cyExample: cles. A nominal baud rate of 20Kbits/s at TCPU = 125ns Consequently, this error (DMEAS) is equal to: (8MHz) leads to LDIVNOM = 25d. 2 / (128*LDIVMIN). LDIVMIN = 25 - 0.15*25 = 21.25 LDIVMIN corresponds to the minimum LIN prescalDMEAS = 2 / (128*LDIVMIN) * 100 = 0.00073% er content, leading to the maximum baud rate, takDQUANT = 1 / (2*16*LDIVMIN) * 100 = 0.0015% ing into account the maximum deviation of +/-15%. 9.5.9.10 Error due to Baud Rate Quantisation LIN Slave systems The baud rate can be adjusted in steps of 1 / (16 * LDIV). The worst case occurs when the "real" For LIN Slave systems (the LINE and LSLV bits baud rate is in the middle of the step. are set), receivers wake up by LIN Synch Break or LIN Identifier detection (depending on the LHDM This leads to a quantization error (DQUANT) equal bit). to 1 / (2*16*LDIVMIN). Hot Plugging Feature for LIN Slave Nodes 9.5.9.11 Impact of Clock Deviation on Maximum Baud Rate In LIN Slave Mute Mode (the LINE, LSLV and RWU bits are set) it is possible to hot plug to a netThe choice of the nominal baud rate (LDIVNOM) work during an ongoing communication flow. In will influence both the quantisation error (DQUANT) this case the SCI monitors the bus on the RDI line and the measurement error (D MEAS). The worst until 11 consecutive dominant bits have been decase occurs for LDIVMIN. tected and discards all the other bits received.
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) 9.5.10 LIN Mode Register Description framing error is detected (if the stop bit is dominant (0) and at least one of the other bits is recessive STATUS REGISTER (SCISR) (1). It is not set when a break occurs, the LHDF bit Read Only is used instead as a break flag (if the LHDM bit=0). Reset Value: 1100 0000 (C0h) It is cleared by a software sequence (an access to the SCISR register followed by a read to the 7 0 SCIDR register). 0: No Framing error TDRE TC RDRF IDLE LHE NF FE PE 1: Framing error detected
Bits 7:4 = Same function as in SCI mode, please refer to Section 9.5.8 SCI Mode Register Description. Bit 3 = LHE LIN Header Error. During LIN Header this bit signals three error types: - The LIN Synch Field is corrupted and the SCI is blocked in LIN Synch State (LSF bit=1). - A timeout occurred during LIN Header reception - An overrun error was detected on one of the header field (see OR bit description in Section 9.5.8 SCI Mode Register Description)). An interrupt is generated if RIE=1 in the SCICR2 register. If blocked in the LIN Synch State, the LSF bit must first be reset (to exit LIN Synch Field state and then to be able to clear LHE flag). Then it is cleared by the following software sequence : an access to the SCISR register followed by a read to the SCIDR register. 0: No LIN Header error 1: LIN Header error detected Note: Apart from the LIN Header this bit signals an Overrun Error as in SCI mode, (see description in Section 9.5.8 SCI Mode Register Description) Bit 2 = NF Noise flag In LIN Master mode (LINE bit = 1 and LSLV bit = 0) this bit has the same function as in SCI mode, please refer to Section 9.5.8 SCI Mode Register Description In LIN Slave mode (LINE bit = 1 and LSLV bit = 1) this bit has no meaning. Bit 1 = Bit 1 = FE Framing error. In LIN slave mode, this bit is set only when a real
Bit 0 = PE Parity error. This bit is set by hardware when a LIN parity error occurs (if the PCE bit is set) in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No LIN parity error 1: LIN Parity error detected CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h)
7
R8 T8 SCID M WAKE PCE PS
0
PIE
Bits 7:3 = Same function as in SCI mode, please refer to Section 9.5.8 SCI Mode Register Description. Bit 2 = PCE Parity control enable. This bit is set and cleared by software. It selects the hardware parity control for LIN identifier parity check. 0: Parity control disabled 1: Parity control enabled When a parity error occurs, the PE bit in the SCISR register is set. Bit 1 = Reserved Bit 0 = Same function as in SCI mode, please refer to Section 9.5.8 SCI Mode Register Description.
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) CONTROL REGISTER 2 (SCICR2) 1: LDIV is updated at the next received character Read/Write (when RDRF=1) after a write to the LPR register Reset Value: 0000 0000 (00 h) Notes: 7 0 - If no write to LPR is performed between the setting of LDUM bit and the reception of the next character, LDIV will be updated with the old value. TIE TCIE RIE ILIE TE RE RWU SBK - After LDUM has been set, it is possible to reset the LDUM bit by software. In this case, LDIV can Bits 7:2 Same function as in SCI mode, please rebe modified by writing into LPR / LPFR registers. fer to Section 9.5.8 SCI Mode Register Description.
Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Notes: - Mute mode is recommended for detecting only the Header and avoiding the reception of any other characters. For more details please refer to Section 9.5.9.3 LIN Reception. - In LIN slave mode, when RDRF is set, the software can not set or clear the RWU bit. Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word. CONTROL REGISTER 3 (SCICR3) Read/Write Reset Value: 0000 0000 (00h)
7
LDUM LINE LSLV LASE LHDM LHIE LHDF
Bit 6:5 = LINE, LSLV LIN Mode Enable Bits. These bits configure the LIN mode:
LINE 0 1 1 LSLV x 0 1 Meaning LIN mode disabled LIN Master Mode LIN Slave Mode
The LIN Master configuration enables: The capability to send LIN Synch Breaks (13 low bits) using the SBK bit in the SCICR2 register. The LIN Slave configuration enables: - The LIN Slave Baud Rate generator. The LIN Divider (LDIV) is then represented by the LPR and LPFR registers. The LPR and LPFR registers are read/write accessible at the address of the SCIBRR register and the address of the SCIETPR register - Management of LIN Headers. - LIN Synch Break detection (11-bit dominant). - LIN Wake-Up method (see LHDM bit) instead of the normal SCI Wake-Up method. - Inhibition of Break transmission capability (SBK has no effect) - LIN Parity Checking (in conjunction with the PCE bit) Bit 4 = LASE LIN Auto Synch Enable. This bit enables the Auto Synch Unit (ASU). It is set and cleared by software. It is only usable in LIN Slave mode. 0: Auto Synch Unit disabled 1: Auto Synch Unit enabled. Bit 3 = LHDM LIN Header Detection Method This bit is set and cleared by software. It is only usable in LIN Slave mode. It enables the Header Detection Method. In addition if the RWU bit in the
0
LSF
Bit 7= LDUM LIN Divider Update Method. This bit is set and cleared by software and is also cleared by hardware (when RDRF=1). It is only used in LIN Slave mode. It determines how the LIN Divider can be updated by software. 0: LDIV is updated as soon as LPR is written (if no Auto Synchronization update occurs at the same time).
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) SCICR2 register is set, the LHDM bit selects the Figure 70. LSF bit set and clear Wake-Up method (replacing the WAKE bit). 11 dominant bits parity bits 0: LIN Synch Break Detection Method 1: LIN Identifier Field Detection Method
LSF bit
Bit 2 = LHIE LIN Header Interrupt Enable This bit is set and cleared by software. It is only usable in LIN Slave mode. 0: LIN Header Interrupt is inhibited. 1: An SCI interrupt is generated whenever LHDF=1. Bit 1= LHDF LIN Header Detection Flag This bit is set by hardware when a LIN Header is detected and cleared by a software sequence (an access to the SCISR register followed by a read of the SCICR3 register). It is only usable in LIN Slave mode. 0: No LIN Header detected. 1: LIN Header detected. Notes: The header detection method depends on the LHDM bit: - If LHDM=0, a header is detected as a LIN Synch Break. - If LHDM=1, a header is detected as a LIN Identifier, meaning that a LIN Synch Break Field + a LIN Synch Field + a LIN Identifier Field have been consecutively received. Bit 0= LSF LIN Synch Field State This bit indicates that the LIN Synch Field is being analyzed. It is only used in LIN Slave mode. In Auto Synchronization Mode (LASE bit=1), when the SCI is in the LIN Synch Field State it waits or counts the falling edges on the RDI line. It is set by hardware as soon as a LIN Synch Break is detected and cleared by hardware when the LIN Synch Field analysis is finished (See Figure 70). This bit can also be cleared by software to exit LIN Synch State and return to idle mode. 0: The current character is not the LIN Synch Field 1: LIN Synch Field State (LIN Synch Field undergoing analysis)
LIN Synch Break
LIN Synch Field
Identifier Field
LIN DIVIDER REGISTERS LDIV is coded using the two registers LPR and LPFR. In LIN Slave mode, the LPR register is accessible at the address of the SCIBRR register and the LPFR register is accessible at the address of the SCIETPR register. LIN PRESCALER REGISTER (LPR) Read/Write Reset Value: 0000 0000 (00h)
7
LPR7 LPR6 LPR5 LPR4 LPR3 LPR2 LPR1
0
LPR0
LPR[7:0] LIN Prescaler (mantissa of LDIV) These 8 bits define the value of the mantissa of the LIN Divider (LDIV):
LPR[7:0] 00h 01h ... FEh FFh Rounded Mantissa (LDIV) SCI clock disabled 1 ... 254 255
Caution: LPR and LPFR registers have different meanings when reading or writing to them. Consequently bit manipulation instructions (BRES or BSET) should never be used to modify the LPR[7:0] bits, or the LPFR[3:0] bits.
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) LIN PRESCALER FRACTION REGISTER will effectively update LDIV and so the clock gen(LPFR) eration. Read/Write 2. In LIN Slave mode, if the LPR[7:0] register is Reset Value: 0000 0000 (00h) equal to 00h, the transceiver and receiver input clocks are switched off. 7 0 LPFR 3 LPFR 2 LPFR 1 LPFR 0
0
0
0
0
Bits 7:4= Reserved. Bits 3:0 = LPFR[3:0] Fraction of LDIV These 4 bits define the fraction of the LIN Divider (LDIV):
LPFR[3:0] 0h 1h ... Eh Fh Fraction (LDIV) 0 1/16 ... 14/16 15/16
Examples of LDIV coding: Example 1: LPR = 27d and LPFR = 12d This leads to: Mantissa (LDIV) = 27d Fraction (LDIV) = 12/16 = 0.75d Therefore LDIV = 27.75d Example 2: LDIV = 25.62d This leads to: LPFR = rounded(16*0.62d) = rounded(9.92d) = 10d = Ah LPR = mantissa (25.620d) = 25d = 1Bh Example 3: LDIV = 25.99d This leads to: LPFR = rounded(16*0.99d) = rounded(15.84d) = 16d
1. When initializing LDIV, the LPFR register must be written first. Then, the write to the LPR register
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont'd) LIN HEADER LENGTH REGISTER (LHLR) LHL[1:0] Read Only 0h Reset Value: 0000 0000 (00 h).
Fraction (57 - THEADER) 0 1/4 1/2 3/4
1h 7
LHL7 LHL6 LHL5 LHL4 LHL3 LHL2 LHL1
0
LHL0
2h 3h
Note: In LIN Slave mode when LASE = 1 or LHDM = 1, the LHLR register is accessible at the address of the SCIERPR register. Otherwise this register is always read as 00h. Bit 7:0 = LHL[7:0] LIN Header Length. This is a read-only register, which is updated by hardware if one of the following conditions occurs: - After each break detection, it is loaded with "FFh". - If a timeout occurs on THEADER, it is loaded with 00h. - After every successful LIN Header reception (at the same time than the setting of LHDF bit), it is loaded with a value (LHL) which gives access to the number of bit times of the LIN header length (THEADER). The coding of this value is explained below: LHL Coding: THEADER_MAX = 57 LHL(7:2) represents the mantissa of (57 - THEADER) LHL(1:0) represents the fraction (57 - THEADER)
LHL[7:2] 0h 1h ... 39h 3Ah 3Bh ... 3Eh 3Fh Mantissa (57 - THEADER) 0 1 ... 56 57 58 ... 62 63 Mantissa (THEADER ) 57 56 ... 1 0 Never Occurs ... Never Occurs Initial value
Example of LHL coding: Example 1: LHL = 33h = 001100 11b LHL(7:3) = 1100b = 12d LHL(1:0) = 11b = 3d This leads to: Mantissa (57 - THEADER) = 12d Fraction (57 - THEADER) = 3/4 = 0.75 Therefore: (57 - THEADER) = 12.75d and THEADER = 44.25d Example 2: 57 - THEADER = 36.21d LHL(1:0) = rounded(4*0.21d) = 1d LHL(7:2) = Mantissa (36.21d) = 36d = 24h Therefore LHL(7:0) = 10010001 = 91h Example 3: 57 - THEADER = 36.90d LHL(1:0) = rounded(4*0.90d) = 4d The carry must be propagated to the matissa : LHL(7:2) = Mantissa (36.90d) + 1= 37d = Therefore LHL(7:0) = 10110000= A0h
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SERIAL COMMUNICATION INTERFACE (Cont'd) Table 21. SCI Register Map and Reset Values
Addr. (Hex.) 0018h 0019h Register Name SCI1SR Reset Value SCI1DR Reset Value SCI1BRR LPR (LIN Slave Mode) Reset Value SCI1CR1 Reset Value SCI1CR2 Reset Value SCI1CR3 Reset Value SCI1ERPR LHLR (LIN Slave Mode) Reset Value SCI1TPR LPRF (LIN Slave Mode) Reset Value 7 TDRE 1 DR7 SCP1 LPR7 0 R8 x TIE 0 LDUM 0 ERPR7 LHL7 0 ETPR7 0 0 6 TC 1 DR6 SCP0 LPR6 0 T8 0 TCIE 0 LINE 0 ERPR6 LHL6 0 ETPR6 0 0 5 RDRF 0 DR5 SCT2 LPR5 0 SCID 0 RIE 0 LSLV 0 ERPR5 LHL5 0 ETPR5 0 0 4 IDLE 0 DR4 SCT1 LPR4 0 M 0 ILIE 0 LASE 0 ERPR4 LHL4 0 ETPR4 0 0 3 OR/LHE 0 DR3 SCT0 LPR3 0 WAKE 0 TE 0 LHDM 0 ERPR3 LHL3 0 ETPR3 LPRF3 0 2 NF 0 DR2 SCR2 LPR2 0 PCE 0 RE 0 LHIE 0 ERPR2 LHL2 0 ETPR2 LPRF2 0 1 FE 0 DR1 SCR1 LPR1 0 PS 0 RWU 0 LHDF 0 ERPR1 LHL1 0 ETPR1 LPRF1 0 0 PE 0 DR0 SCR0 LPR0 0 PIE 0 SBK 0 LSF 0 ERPR0 LHL0 0 ETPR0 LPRF0 0
001Ah
001Bh 001Ch 001Dh
001Eh
001Fh
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9.6 MOTOR CONTROLLER (MTC) 9.6.1 Introduction The ST7 Motor Controller (MTC) can be seen as a Three-Phase Pulse Width Modulator multiplexed on six output channels and a Back Electromotive Force (BEMF) zero-crossing detector for sensorless control of Permanent Magnet Direct Current (PM BLDC) brushless motors. The MTC is particularly suited to driving brushless motors (either induction or permanent magnet types) and supports operating modes like: - Commutation step control with motor voltage regulation and current limitation - Commutation step control with motor current regulation, i.e. direct torque control - Position Sensor or sensorless motor phase commutation control (six-step mode) - BEMF zero-crossing detection with high sensitivity. The integrated phase voltage comparator is directly referred to the full BEMF voltage without any attenuation. A BEMF voltage down to 200 mV can be detected, providing high noise immunity and self-commutated operation in a large speed range. - Realtime motor winding demagnetization detection for fine-tuning the phase voltage masking time to be applied before BEMF monitoring. - Automatic and programmable delay between BEMF zero-crossing detection and motor phase commutation. - PWM generation for three-phase sinewave or three-channel independent PWM signals. Table 22. MTC Functional Blocks
Section Input Detection Block Input Pins Sensorless Mode D Event detection Z Event Detection Demagnetization (D) Event Z Event Generation (BEMF Zero Crossing) Protection for ZH event detection Position Sensor Mode Sampling block Commutation Noise Filter Speed Sensor Mode Tachogenerator Mode Encoder Mode Summary Delay Manager Switched Mode Autoswitched Mode Debug Option Checks and Controls for simulated events Speed Measurement Mode Summary PWM Manager Voltage Mode Over Current Handling in Voltage mode Current Mode Current Feedback Comparator Current feedback amplifier Measurement Window Channel Manager MPHST Phase State Register Emergency Feature Dead Time Generator Programmable Chopper PWM Generator Block Main Features Functional Description Prescaler PWM Operating mode Repetition Down-Counter PWM interrupt generation Timer Re-synchronisation PWM generator initialization and start-up Page 142 142 145 146 147 149 151 153 154 155 158 160 160 161 162 164 165 167 168 171 176 181 181 181 182 182 182 184 184 186 187 187 190 195 196 196 197 197 197 201 201 202 202
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MOTOR CONTROLLER (Cont'd) Table 23. MTC Registers
Register MTIM MTIML MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MCRC MPHST MDFR MCFR MREF MPCR MREP MCPWH MCPWL MCPVH MCPVL MCPUH MCPUL MCP0H MCP0L MDTG MPOL MPWME MCONF MPAR MZFR MSCR Description Timer Counter Register Timer LSB (mode dependent) Capture Zn-1 Register Capture Zn Register Compare Cn+1 Register Demagnetization Reg. An Weight Register Prescaler & Sampling Reg. Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Control Register C Phase State Register D Event Filter Register Current Feedback Filter Register Reference register PWM Control Register Repetition Counter Reg. Compare W Register High Compare W Register Low Compare V Register High Compare V Register Low Compare U Register High Compare U Register Low Compare 0 Register High Compare 0 Register Low Dead Time Generator reg. Polarity Register PWM register Configuration register Parity register Z Event Filter Register Sampling Clock Register Register page Page (RPGS bit) 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 203 203 203 203 203 204 204 204 205 206 208 209 210 212 211 213 214 215 215 215 215 215 216 216 216 216 217 218 219 220 221 222 223
9.6.2 Main Features Two on-chip analog comparators, one for BEMF zero-crossing detection, the other for current regulation or limitation s Seven selectable reference voltages for the hysteresis comparator (0.2 V, 0.6 V, 1 V, 1.5 V, 2 V, 2.5 V, 3.5 V) and the possibility to select an external reference pin (MCVREF). s 8-bit timer (MTIM) with three compare registers and two capture features, which may be used as the Delay manager of a speed measurement unit s Measurement window generator for BEMF zero-crossing detection s Filter option for the zero-crossing detection. s Auto-calibrated prescaler with 16 division steps s 8x8-bit multiplier s Phase input multiplexer s Sophisticated output management: - The six output channels can be split into two groups (high & low) - The PWM signal can be multiplexed on high, low or both groups, alternatively or simultaneously, for six-step motor drives - 12-bit PWM generator with full modulation capability (0 and 100% duty cycle), edge or center-aligned patterns - Dedicated interrupt for PWM duty cycles updating and associated PWM repetition counter. - Programmable deadtime insertion unit. - Programmable High frequency Chopper insertion and high current PWM outputs for direct optocoupler drives. - The output polarity is programmable channel by channel. - A programmable bit (active low) forces the outputs in HiZ, Low or High state, depending on option byte 1 (refer to "ST7FMC Device Configuration And Ordering Information" section). - An "emergency stop" input pin (active low) asynchronously forces the outputs in HiZ, Low or High state, depending on option byte 1 (refer to "ST7FMC Device Configuration And Ordering Information" section).
s
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.3 Application Example: PM BLDC motor drive This example shows a six-step command sequence for a 3-phase permanent magnet DC brushless motor (PM BLDC motor). Figure 72 shows the phase steps and voltage, while Table 24 shows the relevant phase configurations. To run this kind of motor efficiently, an autoswitching mode has to be used, i.e. the position of the rotor must self-generate the powered winding commutation. The BEMF zero crossing (Z event) on the non-excited winding is used by the MTC as a rotor position sensor. The delay between this event and the commutation is computed by the MTC and the hardware commutation event C n is automatically generated after this delay. After the commutation occurs, the MTC waits until the winding is completely demagnetized by the free-wheeling diode: during this phase the winding is tied to 0V or to the HV high voltage rail and no BEMF can be read. At the end of this phase a new BEMF zero-crossing detection is enabled.
The end of demagnetization event (D), is also detected by the MTC or simulated with a timer compare feature when no detection is possible. The MTC manages these three events always in the same order: Z generates C after a delay computed in realtime, then waits for D in order to enable the peripheral to detect another Z event. The BEMF zero-crossing event (Z), can also be detected by the MTC or simulated with a timer compare feature when no detection is possible. The speed regulation is managed by the microcontroller, by means of an adjustable reference current level in case of current control, or by direct PWM duty-cycle adjustment in case of voltage control.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 71. Chronogram of Events (in Autoswitched Mode) .
CH event ZH or ZS event DH event DS event Cn processing Wait for Cn Wait for Dn Wait for Z T Zn Dn Cn
t Voltage on phase A
Voltage on phase B
Voltage on phase C BEMF sampling P signal when sampled (Output of the V DD analog MUX) VREF (Threshold value for VSS Input comparator)
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 72. Example of Command Sequence for 6-step Mode (typical 3-phase PM BLDC Motor Control)
Step Switch 0 1 I1 2 3 I3 4 5 Node A
HV HV/2 0
1
2
3
4
5
6
1
2
3
HV
T0
T2 B I6
T4
I4
A I5
I2
C
T1
T3
T5
B
HV HV/2 0 HV HV/2 0
C
Note: Control & sampling PWM influence is not represented on these simplified chronograms. 1 2 3 4 5
HV
6
C2 D2
HV/2
C4
Superimposed voltage (BEMF induced by rotor) - approx. HV/2 (PWM on) - approx. 0V (PWM off)
0V
Z2 Demagnetization Commutation delay
D5 Z 5 t PWM off pulses
Wait for BEMF = 0
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MOTOR CONTROLLER (Cont'd) All detections of Zn events are done during a short measurement window while the high side switch is turned off. For this reason the PWM signal is applied on the high side switches. When the high side switch is off, the high side winding is tied to 0V by the free-wheeling diode, Table 24. Step Configuration Summary
Configuration BEMF BEMF Phase state edge input register Current direction High side Low side OO[5:0] bits in MPHST register Measurement done on: IS[1:0] bits in MPHST register Back EMF shape CPB bit in MCRB register (ZVD bit = 0) Voltage on measured point at the start of demagnetization Step 1 A to B T0 T3 001001 MCIC 10 Falling 0 0V 2 A to C T0 T5 100001 MCIB 01 Rising 1 HV 3 B to C T2 T5 100100 MCIA 00 Falling 0 0V 4 B to A T2 T1 000110 MCIC 10 Rising 1 HV 5 C to A T4 T1 010010 MCIB 01 Falling 0 0V 6 C to B T4 T3 011000 MCIA 00 Rising 1 HV
the low side winding voltage is also held at 0V by the low side ON switch and the complete BEMF voltage is present on the third winding: detection is then possible.
Hardware-simulated
demagnetization
Hardware or
HDM-SDM bits in MCRB register
10
11
10
11
10
11
Demagnetization
PWM side selection to accelerate Low Side High Side Low Side High Side Low Side High Side demagnetization switch Driver selection to accelerate demagnetization
T3
T0
T5
T2
T1
T4
For a detailed description of the MTC registers, see Section 9.6.13. 9.6.4 Application Example: AC Induction Motor Drive Although the command sequence is rather different between a PM BLDC and an AC three-phase induction motor, the Motor Controller can be configured to generate three-phase sinusoidal voltages. A timer with three independent PWM channels is available for this purpose. Based on each of the PWM reference signal, two complemented PWM signals with deadtime are generated on the output pins (6 in total), to drive directly an inverter with triple half bridge topology.
The variable voltage levels to be applied on the motor terminals come from continuously varying duty cycle, from one PWM period to the other (refer to Figure 73 on page 140). The PWM counter generates a dedicated Update event (U event) which: - updates automatically the compare registers setting the duty cycle to avoid time critical issues and ensure glitchless PWM operation. - generates a dedicated U interrupt in which the values for the next coming update event are loaded in compare preload registers. The shape of the output voltage (voltage, frequency, sinewave, trapezoid, ...) is completely managed by the applicative software, in charge of computing the compare values to be loaded for a given PWM duty-cycle (refer to Figure 74).
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MOTOR CONTROLLER (Cont'd) Finally, the PWM modulated voltage generated by the power stage is smoothed by the motor inductance to get sinusoidal currents in the stator windings. The induction motor being asynchronous, there is no need to synchronize the rotor position to the sinewave generation phase in most of the applications. Part of the MTC dedicated to delay computation and event sampling can thus be reconfigured to
perform speed acquisition of the most common speed sensor, without the need of an additional standard timer. This speed measurement timer with clear-on-capture and clock prescaler auto-setting allows to keep the CPU load to a minimum level while taking benefit of the embedded input comparator and edge detector.
Figure 73. Complementary PWM generation for three-phase induction motor (1 phase represented)
U event Compare preload register processing
MCMP0 MCMPU
PWM generator counter PWM Ref Signal T0 T1
Dead time insertion
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MOTOR CONTROLLER (Cont'd) Figure 74. Typical command signals of a three-phase induction motor
HV
Phase A *
T0 T2 B T4
Phase B *
Phase C *
PWM period PWM output PWM output Duty Cycle 51% 50% 49% PWM output Duty Cycle 1% 0% 1% Duty Cycle 99% 100% 99%
A C
T1
T3
T5
* These simplified chronograms represent the phase voltages after low-pass filtering of the PWM outputs reference signals
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.5 Functional Description The MTC can be split into five main parts as shown in the simplified block diagram in Figure 75. Each of these parts may be configured for different purposes: s INPUT DETECTION BLOCK with a comparator, an input multiplexer and an incremental encoder interface, which may work as: - A BEMF zero-crossing detector - A Speed Sensor Interface s The DELAY MANAGER with an 8/16-bit timer and an 8x8 bit multiplier, which may work as a: - 8-bit delay manager - Speed Measurement unit s The PWM MANAGER, including a measurement window generator, a mode selector and a current comparator. s The CHANNEL MANAGER with the PWM multiplexer, polarity programming, deadtime insertion and high frequency chopping capability and emergency HiZ configuration input. s The THREE-PHASE PWM GENERATOR with 12-bit free-running counter and repetition counter. 9.6.6 Input Detection Block This block can operate in Position sensor mode, in sensorless mode or in Speed Sensor mode. The mode is selected via the SR bit in the MCRA register and the TES[1:0] bits in MPAR register (refer
to Table 35 for set-up information). The block diagram is shown in Figure 76 for the Position Sensor/Sensorless modes (TES[1:0] = 00) and in Figure 86 for the Speed Sensor mode (TES[1:0] = 01, 10, 11). 9.6.6.1 Input Pins The MCIA, MCIB and MCIC input pins can be used as analog or as digital pins. - In sensorless mode, the analog inputs are used to measure the BEMF zero crossing and to detect the end of demagnetization if required. - In sensor mode, the analog inputs are used to get the Hall sensor information. - In speed sensor mode (e.g. tachogenerator), the inputs are used as digital pins. When using an AC tachogenerator, a small external circuit may be needed to convert the incoming signal into a square wave signal which can be treated by the MTC. Due to the presence of diodes, these pins can permanently support an input current of 5mA. In sensorless mode, this feature enables the inputs to be connected to each motor phase through a single resistor. A multiplexer, programmed by the IS[1:0] bits in the MPHST register selects the input pins and connects them to the control logic in either sensorless or tachogenerator mode. In encoder mode, it is mandatory to connect sensor digital outputs to the MCIA and MCIB pins.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 75. Simplified MTC Block Diagram DELAY MANAGER or SPEED MEASURE UNIT (not represented)
DELAY WEIGHT CAPTURE Zn MTIM TIMER BEMF ZERO-CROSSING DETECTOR BEMF=0 [Z] TACHO Int/Ext
MCIA MCIB MCIC MCVREF
DELAY = WEIGHT x Zn
=? COMMUTE [C]
Encoder Unit
INPUT DETECTION
MCO5 PHASE
MEASUREMENT WINDOW GENERATOR
(I) CURRENT VOLTAGE (V) (I) (V) MODE
MCO4 MCO3 MCO2 MCO1 MCO0 U, V, W Phases CFAV bit
OAON bit
NMCES + OAP OAN OAZ MCCFI VDD MCCREF (V) R1 R2
-
PWM MANAGER
ADC
Phase U
CHANNEL MANAGER
12-bit counter 1 (V) PCN bit
C
(I)
12-bit THREE-PHASE PWM GENERATOR
R3
Phase U Phase V Phase W [Z] : Back EMF Zero-crossing event Zn : Time elapsed between two consecutive Z events [C] : Commutation event Cn : Time delayed after Z event to generate C event (I): Current mode (V): Voltage mode
MCPWMU MCPWMV MCPWMW
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MOTOR CONTROLLER (Cont'd) Figure 76. Input Stage in Sensorless or Sensor Mode (bits TES[1:0] = 00)
Input Block Input Comparator Block MPHST Register Inputn Sel Reg MCIA 00 MCIB B MCIC C MCVREF 111 V REF IS[1:0]
1 SR bit
Event Detection
MDFR Register DWF[3:0] MZFR Register
2
A
CS,H
MCRA Register
ZWF[3:0]
01
+
DQ
Sample
10
CP
DS,H CS,H
1
2
VR[2:0] MCRC Register fSCF
Sampling frequency 12-bit PWM generator Signal U
Notes:
Reg Regn I V Updated/Shifted on R Updated with Regn+1 on C
MCRC Register MCONF Register SPLG bit DS[3:0] bits
I V
MCRA Register V0C1 bit MCRB Register MPOL Register MCRA Register CPBn bit* Z Event Generation MPOL Register DS,H CS,H Sample
2
Current Mode Voltage Mode
ZVD bit
PZ bit
events: C Commutation Z BEFM Zero-crossing DS,H End Of Demagnetization E Emergency Stop R+/- Ratio Updated (+1 or -1) O Multiplier Overflow
1
REO bit
or or or
Branch taken after C event Branch taken after D event
to ZH Generation
2
D Event Generation
1
or
MCRA Register
SR bit
to DH Generation CPBn bit* HDMn bit* MCRB Register * = Preload register, changes taken into account at next C event
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MOTOR CONTROLLER (Cont'd) 9.6.6.2 Sensorless Mode This mode is used to detect BEMF zero crossing and end of demagnetization events. The analog phase multiplexer connects the nonexcited motor winding to an analog 100mV hysteresis comparator referred to a selectable reference voltage. IS[1:0] bits in MPHST register allow to select the input which will be drive to the comparator (either MCIA, B or C). Be careful that the comparator is OFF until CKE and/or DAC bit are set in MCRA register. The VR[2:0] bits in the MCRC register select the reference voltage from seven internal values depending on the noise level and the application voltage supply. The reference voltage can also be set externally through the MCVREF pin when the VR[2:0] bits are set. Table 25. Threshold voltage setting
VR2 1 1 1 1 0 0 0 0 VR1 1 1 0 0 1 1 0 0 VR0 1 0 1 0 1 0 1 0 Vref voltage threshold Threshold voltage set by external MCVREF pin 3.5V* 2.5V* 2V* 1.5V* 1V* 0.6V* 0.2V*
*Typical value for VDD=5V. BEMF detections are performed during the measurement window, when the excited windings are free-wheeling through the low side switches and diodes. At this stage the common star connection
voltage is near to ground voltage (instead of VDD/2 when the excited windings are powered) and the complete BEMF voltage is present on the non-excited winding terminal, referred to the ground terminal. The zero crossing sampling frequency is then defined, in current mode, by the measurement window generator frequency (SA[3:0] bits in the MPRSR register) or, in voltage mode, by the PWM generator frequency and phase U duty cycle. During a short period after a phase commutation (C event), the winding where the back-emf will be read is no longer excited but needs a demagnetisation phase during which the BEMF cannot be read. A demagnetization current goes through the free-wheeling diodes and the winding voltage is stuck at the high voltage or to the ground terminal. For this reason an "end of demagnetization event" D must be detected on the winding before the detector can sense a BEMF zero crossing. For the end-of-demagnetization detection, no special PWM configuration is needed, the comparator sensing is done at a selectable frequency (fSCF), see Table 83. So, the three events: C (commutation), D (demagnetization) and Z (BEMF zero crossing) must always occur in this order in autoswitched mode when hard commutation is selected. The comparator output is processed by a detector that automatically recognizes the D or Z event, depending on the CPB or ZVD edge and level configuration bits as described in Table 30. To avoid wrong detection of D and Z events, a blanking window filter is implemented for spike filtering. In addition, by means of an event counter, software can filter several consecutive events up to a programmed limit before generating the D or Z event internally. This is shown in Figure 77 and Figure 78.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.6.3 D Event detection In sensorless mode, the D Window Filter becomes active after each C event. It blanks out the D event during the time window defined by the DWF[3:0] bits in the MDFR register (see Table 26). The reset value is 200s. This Window Filter becomes active after both hardware and software C events. The D Event Filter becomes active after the D Window Filter. It counts the number of consecutive D events up to a limit defined by the DEF[3:0] bits in the MDFR register. The reset value is 1. The D bit is set when the counter limit is reached. Sampling is done at a selectable frequency (fSCF ), see Table 83. The D event filter is active only for a hardware D event (D H). For a simulated (DS) event, it is forced to 1. Figure 77. D Window and Event Filter Flowchart
C
C to D window filDWF3 DWF2 DWF1 DWF0 ter in Sensorless SR=1 Mode (SR=0) 0 0 0 0 5 s 0 0 0 1 10 s 0 0 1 0 15 s 0 0 1 1 20 s 0 1 0 0 25 s 0 1 0 1 30 s 0 1 1 0 35 s 0 1 1 1 40 s 1 0 0 0 60 s 1 0 0 1 80 s 1 0 1 0 100 s 1 0 1 1 120 s 1 1 0 0 140 s 1 1 0 1 160 s 1 1 1 0 180 s 1 1 1 1 200 s
Note: Times are indicated for 4 MHz fPERIPH Table 27. D Event filter Setting
No End of Blanking Window ?
WINDOW FILTER
DEF3 DEF2 DEF1 DEF0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
D event Limit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SR=1
Yes Sampling
0 0
EVENT FILTER
No D Event ? Yes
0 0 0 0 1
Reset counter
No
1 Limit=1? 1 1
Increment counter Yes
1 1
No
1 Counter=Limit? 1
Yes Set the D bit
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No D Event Filter
No Window Filter after C event
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.6.4 Z Event Detection In sensorless mode, the Z window filter becomes active after each D event. It blanks out the Z event during the time window defined by the ZWF[3:0] bits in the MZFR register (see Table 28). The reset value is 200s. This Window Filter becomes active after both hardware and software C events. The Z Event Filter becomes active after the Z Window Filter. It counts the number of consecutive Z events up to a limit defined by the ZEF[3:0] bits in the MZFR register. The reset value is 1. The Z bit is set when the counter limit is reached. Sampling is done at a selectable frequency (fSCF), see Table 83. The Z event filter is active only for a hardware Z event (ZH). For a simulated (ZS) event, it is forced to 1. Figure 78. Z Window and Event Filter Flowchart
D
Table 28. Z Window filter Setting
D to Z window filZWF3 ZWF2 ZWF1 ZWF0 ter in Sensorless Mode (SR=0) 0 0 0 0 5 s 0 0 0 1 10 s 0 0 1 0 15 s 0 0 1 1 20 s 0 1 0 0 25 s 0 1 0 1 30 s 0 1 1 0 35 s 0 1 1 1 40 s 1 0 0 0 60 s 1 0 0 1 80 s 1 0 1 0 100 s 1 0 1 1 120 s 1 1 0 0 140 s 1 1 0 1 160 s 1 1 1 0 180 s 1 1 1 1 200 s SR=1
No Window Filter after D event
No
End of Blanking Window ? Yes Sampling
WINDOW FILTER
Note: Times are indicated for 4 MHz fPERIPH Table 29. Z Event filter Setting
ZEF3 0 ZEF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ZEF1 ZEF0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z event Limit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
No
Z Event ? No
EVENT FILTER
Yes
0 0 0 0 0
Reset counter
Limit=1?
0 0
Increment counter Yes No
1 1
Counter=Limit?
1 1 1
Yes Set the Z bit
1 1 1
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MOTOR CONTROLLER (Cont'd) Table 30 shows the event control selected by the ZVD and CPB bits. In most cases, the D and Z events have opposite edge polarity, so the ZVD bit is usually 0. Table 30. ZVD and CPB Edge Selection Bits
ZVD bit CPB bit DWF 0 0 DEF Event generation vs input data sampled ZWF ZEF
C
DWF 0 1 DEF
DH
ZWF ZEF
Z
C
DWF 1 0 DEF
DH
ZWF
Z
ZEF
C
DWF 1 1 DEF
DH
ZWF ZEF
Z
C
DH
Z
Note: The ZVD bit is located in the MPOL register, the CPB bit is in the MCRB register.
Legend: DWF= D window filter DEF= D event filter ZWF = Z window filter ZEF = Z event filter Refer also to Table 34 on page 158.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.6.5 Demagnetization (D) Event At the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. The voltage on the non-excited winding terminal goes from one of the power rail voltages to the common star connection voltage plus the BEMF voltage. In some cases (if the BEMF voltage is positive and the free-wheeling diodes are at ground for example) this end of demagnetization can be seen as a voltage edge on the selected MCIx input and it is called a hardware demagnetization event DH. See Table 30. The D event filter can be used to select the number of consecutive D events needed to generate the DH event. If enabled by the HDM bit in the MCRB register, the current value of the MTIM timer is captured in register MDREG when this event occurs in order to be able to simulate the demagnetization phase for the next steps. When enabled by the SDM bit in the MCRB register, demagnetization can also be simulated by comparing the MTIM timer with the MDREG register. This kind of demagnetization is called simulated demagnetization DS. If the HDM and SDM bits are both set, the first event that occurs, triggers a demagnetization event. For this to work correctly, a DS event must Figure 79. D Event Generation Mechanism
DS,H C Sample SPLG bit MCRC Register
2 1
or
not precede a DH event because the latter could be detected as a Z event. Simulated demagnetization can also be always used if the HDM bit is reset and the SDM bit is set. This mode works as a programmable masking time between the C H and Z events. To drive the motor securely, the masking time must be always greater than the real demagnetization time in order to avoid a spurious Z event. When an event occurs, (either DH or DS) the DI bit in the MISR register is set and an interrupt request is generated if the DIM bit of register MIMR is set. Caution 1: Due to the alternate automatic capture and compare of the MTIM timer with MDREG register by DH and DS events, the MDREG register should be manipulated with special care. Caution 2: Due to the event generation protection in the MZREG, MCOMP and MDREG registers for Soft Event generation ( See "Built-in Checks and Controls for simulated events" on page 171.), the value written in the MDREG register in soft demagnetisation mode (SDM=1) is checked by hardware after the C event. If this value is less than or equal to the MTIM counter value at this moment, the Software demagnetisation event is generated immediately and the MTIM current value overwrites the value in the MDREG register to be able to reuse the right demagnetisation time for another simulated event generation.
To Z event detection
MTIM [8-bit Up Counter] 8 DH MDREG [Dn] Compare
CPBn bit*
HDMn bit* SR bit
MCRB Register
MCRB Register SDM* bit DWF[3:0] DEF[3:0] DH MDFR Register
MCRA Register
DS D
DS DH HDM bit SDM bit
F(x)
D = DH & HDM bit + DS & SDM bit To interrupt generator Register updated on R event * = Preload register, changes taken into account at next C event
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MOTOR CONTROLLER (Cont'd) Table
HDM bit
31.
Demagnetisation
Meaning
(D)
Event
CPB bit = 1 CPB bit = 0
D = DS = Output Compare [MDREG, MTIM registers] Undershoot due to motor parasite or first sampling 2
HVV HV
Weak / null undershoot and BEMF positive 2
HVV
5 DS CH
CH Simulated Mode 0 (SDM bit =1 and HDM bit = 0)
HV/2
DS
(*)
HV/2
DS
CH
HV/2
(*)
(*)
0V
0V
0V
Z D = DH + D S
Z
Z D = DH (Hardware detection only)
(Hardware detection or Output compare true) Undershoot due to Weak / null motor parasite or first undershoot and sampling BEMF positive 2 2
HV HV
5
HV
1
Hardware/Simulated Mode (SDM bit = 1 and HDM bit = 1)
HV/2
CH DS
CH
(*)
HV/2
DS
CH
HV/2
(*)
(*)
0V
0V
0V
DH
Z
Z
DH
Z
(*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF)
Generation (example for ZVD=0)
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MOTOR CONTROLLER (Cont'd) 9.6.6.6 Z Event Generation (BEMF Zero Crossing) When both C and D events have occurred, the PWM may be switched to another group of outputs (depending on the OS[2:0] bits in the MCRB register) and the real BEMF zero crossing sampling can start (see Figure 85). After Z event, the PWM can also be switched to another group of outputs before the next C event. A BEMF voltage is present on the non-powered terminal but referred to the common star connection of the motor whose voltage is equal to VDD/2. When a winding is free-wheeling (during PWM offtime) its terminal voltage changes to the other power rail voltage, this means if the PWM is applied on the high side driver, free-wheeling will be done through the low side diode and the terminal will be 0V. This is used to force the common star connection to 0V in order to read the BEMF referred to the ground terminal. Consequently, BEMF reading (i.e. comparison with a voltage close to 0V) can only be done when the PWM is applied on the high side drivers. When the BEMF signal crosses the threshold voltage close to zero, it is called a hardware zero-crossing event ZH. A filter can be implemented on the ZH event detection (see Figure 81). The Z event filter register (MZFR) is used to select the number of consecutive Z events needed to generate the ZH event. Alternatively, the PZ bit can be used to enable protection as described in Figure 81. on page 153 For this reason the MTC outputs can be split in two groups called LOW and HIGH and the BEMF reading will be done only when PWM is applied on one of these two groups. The REO bit in the MPOL register is used to select the group to be used for
BEMF sensing (high side group). It has to be configured whatever the sampling mode. When enabled by the HZ bit in MCRC register, the current value of the MTIM timer is captured in register MZREG when this event occurs in order to be able to compute the real delay in the delay manager part for hardware commutation but also to be able to simulate zero-crossing events for other steps. When enabled by the SZ bit set in the MCRC register, a zero-crossing event can also be simulated by comparing the MTIM timer value with the MZREG register. This kind of zero-crossing event is called simulated zero-crossing ZS. If both HZ and SZ bits are set in MCRC register, the first event that occurs, triggers a zero-crossing event. Depending on the edge and level selection (ZVD and CPB) bits and when PWM is applied on the correct group, a BEMF zero crossing detection (either ZH or ZS) sets the ZI bit in the MISR register and generates an interrupt if the ZIM bit is set in the MIMR register. Caution 1: Due to the alternate automatic capture and compare of the MTIM timer with MZREG register by ZH and ZS events, the MZREG register should be manipulated with special care. Caution 2: Due to the event generation protection in the MZREG, MCOMP and MDREG registers for Soft Event generation, the value written in the MZREG register in simuated zero-crossing mode (SZ=1) is checked by hardware after the D (either DH or DS) event. If this value is less than or equal to the MTIM counter value at this moment, the simulated zero-crossing event is generated immediately and the MTIM current value overwrites the value in the MZREG register. See "Built-in Checks and Controls for simulated events" on page 171. The Z event also triggers some timer/multiplier operations, for more details see Section 9.6.7
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MOTOR CONTROLLER (Cont'd) Figure 80. Z Event Generation
MCRB Register MPOL Register MCRA Register CPBn bit* MPOL Register DS,H CS,H Sample
2 1
ZVD bit
PZ bit
MTIM [8-bit Up Counter] (MSB) 8 ZH MZREG [Zn]
REO bit
or or or
SPLG bit DS[3:0] bits ZS ZH SZ bit HZ bit
MCRC Register HZ bit To D detection
MCRC Register SZ bit ZWF[3:0] ZEF[3:0] MZFR register
Compare MZFR register ZWF[3:0] ZS
Z = ZH& HZ bit+ ZS & SZ bit F(x)
ZH
Z
To interrupt generator Register updated on R event * = Preload register, changes taken into account at next C event
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MOTOR CONTROLLER (Cont'd) 9.6.6.7 Protection for ZH event detection To avoid an erroneous detection of a hardware zero-crossing event, a filter can be enabled by setting the PZ bit in the MCRA register. This filter will ensure the detection of a ZH event on an edge transition between D event and ZH event. Without this protection, ZH event detection is done directly on the current sample in comparison with the expected state at the output of the phase comparator. For example, if a falling edge transition (meaning a transition from 1 to 0 at the output of the phase comparator) is configured for ZH event through the CPB bit in MCRB register, then, the state 0 is expected at the comparator output and Figure 81. Protection of ZH event detection.
V Voltage mode I Current mode Rz Rising edge zero-crossing Fz Falling edge zero-crossing C Commutation event Falling/Rising Edge MCRB register MPOL register ZVD bit CPB* bit
once this state is detected, the ZH event is generated without any verification that the state at the comparator output of the previous sample was 1. The purpose of this protection filter is to be sure that the state of the comparator output at the sample before was really the opposite of the current state which is generating the ZH event. With this filter, the ZH event generation is done on edge transition level comparison. This filter is not needed in sensor mode (SR=1) and for simulated zero-crossing event (ZS) generation. When the PZ bit is set, the Z event filter ZEF[3:0] in the MZFR register is ignored.
Fz C
Current sample
Previous sample
+
D
R
Q
D
R
Q
Phase Comparator CP S Q CP S Q Fz Direct/Filter PZ MCRA register bit 1
F C Rz
Z
Rz D D R Q
V Sampling clock I
Instantaneous edge CP S Q
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MOTOR CONTROLLER (Cont'd) 9.6.6.8 Position Sensor Mode In position sensor mode (SR=1 in MCRA register), the rotor position information is given to the peripheral by means of logical data on the three inputs MCIA, MCIB and MCIC (Hall sensors). For each step one of these three inputs is selected (IS[1:0] bits in register MPHST) in order to detect the Z event. Be careful that the phase comparator is OFF until CKE and /or DAC bits are set in MCRA register. In sensor mode, Demagnetization and the related features (such as the special PWM configuration, DS or DH management, programmable filter) are not available (see Table 32) Table 32. Demagnetisation access
SR bit MCRA register 1 0 Demagnetisation feature availabilty NO YES
In sensor mode configuration the rotor detection doesn't need a particular phase configuration to perform the measurement and a Z event can be read from any detection window. The sampling is
done at a selectable frequency (fSCF), see Table 83. This means that Z event position sensoring is more precise than it is in sensorless mode. There is no minimum off time required for current control PWM in sensor mode so the minimum off time is set automatically to 0s as soon as the SR bit is set in the MCRA register and a true 100% duty cycle can be set in the PWM compare U register for the PWM generation in voltage mode. In Sensor mode, the ZEF[3:0] bits in the MZFR register are active and can be used to define the number of consecutive Z samples needed to generate the active event. Procedure for reading sensor inputs in Direct Access mode: In Direct Access mode, the sensors can be read either when the clock are enabled or disabled (depending on CKE it in MCRA register). To read the sensor data the following steps have to be performed: 1. Select Direct Access Mode (DAC bit in MCRA register) 2. Select the appropriate MCIx input pin by means of the IS[1:0] bits in the MPHST register 3. Read the comparator output (HST bit in the MREF register)
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MOTOR CONTROLLER (Cont'd) 9.6.6.9 Sampling block For a full digital solution, the phase comparator output sampling frequency is the frequency of the PWM signal applied to the switches and the sampling for the Z event detection in sensorless mode is done at the end of the off time of this PWM signal to avoid to have to re-create a virtual ground because when the PWM signal is off, the star point is at ground due to the free-wheeling diode. That's why, the sampling for Z event detection is done by default during the OFF-state of the PWM signal and therefore at the PWM frequency. In current mode, this PWM signal is generated by a combination of the output of the measurement window generator (SA[3:0] bits), the output of the current comparator and a minimum OFF time set by the OT[3:0] bits for system stabilisation. In voltage mode, this PWM signal is generated by the 12-bit PWM generator signal in the compare U register with still a minimum OFF time required if the sampling is done at the end of the OFF time of the PWM signal for system stabilisation. The PWM signal is put OFF as soon as the current feedback reaches the current input limitation. This can add an OFF time to the one programmed with the 12bit Timer. For D event detection in sensorless mode, no specific PWM configuration is needed and the sampling frequency (fSCF, see Table 83) is completely independent from the PWM signal. In sensor mode, the D event detection is not needed as the MCIA, MCIB and MCIC pins are the digital signals coming from the hall sensors so no specific PWM configuration is needed and the sampling for the Z detection event is done at fSCF, completely independent from the PWM signal. In sensorless mode, if a virtual ground is created by the addition of an external circuit, sampling for the Z event detection can be completely independent from the PWM signal applied to the switches. Setting the SPLG bit in the MCRC register allows a sampling frequency of fSCF for Z event detection independent from the PWM signal after getting the D (end of demagnetisation) event. This means that the sampling order is given either during the ON time or the OFF time of the PWM signal. As soon as the SPLG bit is set in the MCRC register, the minimum OFF time needed for the PWM signal in current mode is set to 0s and a true 100% duty
cycle can be set in the 12-bit PWM generator compare register in voltage mode. Specific applications can require sampling for the Z event detection only during the ON time of the PWM signal. This can happen when the PWM signal is applied only on the low side switches for Z event detection. In this case, during the OFF time of the PWM signal, the phase voltage is tied to the application voltage V and no back-EMF signal can be seen. During the ON time of the PWM signal, the phase voltage can be compared to the neutral point voltage and the Z event can be detected. Therefore, it is possible to add a programmable delay before sampling (which is normally done when the PWM signal is switched ON) to perform the sampling during the ON time of the PWM signal. This delay is set with the DS [3:0] bits in the MCONF register. Table 33. Delay length before sampling
DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Delay added to sample at Ton No delay added. Sample during Toff 2.5 s 5 s 7.5 s 10 s 12.5 s 15 s 17.5 s 20 s 22.5 s 25 s 27.5 s 30 s 32.5 s 35 s 37.5 s
Note: Times are indicated for 4 MHz fPERIPH As soon as a delay is set in the DS[3:0] bits, the minimum OFF time for the PWM signal is no longer required and it is automatically set to 0s in current mode in the internal sampling clock and a true 100% duty cycle can be set in the 12-bit PWM generator compare U register if needed.
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MOTOR CONTROLLER (Cont'd) Depending on the frequency and the duty cycle of the PWM signal, the delay inserted before sampling could cause it sample the signal OFF time instead of the ON time. In this case an interrupt can be generated and the sample will not be taken into acount. When a sample occurs outside the PWM signal ON time, the SOI bit in the MCONF register is set and an interrupt request is generated if the SOM bit is set in the MCONF register. This interrupt is enabled only if a delay value has been set in the DS[3:0] bits. In this case, the sampling is done at the PWM frequency but only during the ON time of the PWM signal. Figure 82 and Figure 83 shows in detail the generation of the sampling order when the delay is added.
For complete flexibility, the possibility of sampling at 1 MHz frequency during the ON time of the PWM signal is also available when the SPLG bit is set as if there is a delay value in the DS[3:0] bits. This means that when the sampling is to be performed, after the delay a 1 MHz sampling window is opened until the next OFF time of the PWM signal. The Sampling Out interrupt will be generated if the delay added is longer than the duty cycle of the PWM signal. As the SPLG bit is set and a value has been put in the DS[3:0] bits, no minimum off time is required for the PWM signal and it is automatically set to 0s in current mode. A true 100% duty cycle can be also set in the 12-bit Timer in voltage mode. Figure 84 shows in detail the sampling at 1 MHz during ON time.
Figure 82. Adding the Delay to sample during ON time for Z detection
TSampling New sample
DS[3:0] PWM signal PWM OFF time
DS[3:0]
Current sample
Figure 83. Sampling Out interrupt generation
TSampling SO DS[3:0] PWM signal PWM OFF time New sample during next OFF time. Sample not taken into account. SO interrupt generated. To interrupt generator
Current sample
SO
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MOTOR CONTROLLER (Cont'd) In conclusion, there are 4 sampling types that are available for Z event detection in sensorless mode. 1. Sampling at the end of the OFF time of the PWM signal at the PWM frequency 2. Sampling, at a programmable frequency independent of the PWM state (either during ON time or OFF time of the signal). Sampling is done at fSCF, see Table 83. 3. Sampling during the ON time of the PWM signal by adding a delay at PWM frequency 4. Sampling, at a programmable frequency during the ON time (addition of a programmable delay) of the PWM signal. Sampling is done at fSCF, see Table 83. Note 1: The sampling type is applied only for Z event detection after the D event has occured. Whatever the sampling type for Z event detection, the sampling of the signal for D event detection is Figure 84. Sampling during ON time at fSCF fSCF
during ON time
always done at the selected fSCF frequency (see Table 83), independently of the PWM signal (either during ON or OFF time). Table 34 explains the different sampling types in sensorless and in sensor mode. Note 2: When the MOE bit in the MCRA register is reset (MCOx outputs in reset state), and the SR bit in the MCRA register is reset (sensorless mode) and the SPLG bit in the MCRC register is reset (sampling at PWM frequency) then, depending on the state of the ZSV bit in the MSCR register, Z event sampling can run or be stopped (and D event is sampled). Note 3: When BEMF sampling is performed at the end of the PWM signal off-time, the inputs in OFFstate are grounded or put in HiZ as selected by the DISS bit in the MSCR register. Note 4: The ZEF[3:0] event counter in the MZFR register is active in all configurations.
DS[3:0] PWM signal PWM OFF state
DS[3:0]
Current sample
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MOTOR CONTROLLER (Cont'd) 9.6.6.10 Commutation Noise Filter For D event detection and for Z event detection (when SPLG bit is set while DS[3:0] bits are reset), sampling is done at fSCF either during the PWM ON or OFF time ("Sampling block" on page 155). To avoid any erroneous detection due to PWM commutation noise, an hardware filter of 1s (for fPERIPH = 4Mhz) when PWM is put ON and when PWM is put OFF has been implemented. This
means that, with sampling at 1MHz (1s), due to this filter, 1 sample are ignored directly after the commutation. This filter is active all the time for the D event and it is active for the Z event when the SPLG bit is set and DS[3:0] bits are cleared (meaning that the Z event is sampled at high frequency either during the PWM ON or OFF time).
Table 34. Sensor/sensorless mode and D & Z event selection
SR SPLG DS[3:0] bit bit bits Mode Sampling Event detection behaviour for OS[2:0] sampling clock Z event bits use detection At the end of D: fSCF the off time of Enabled Z: SA&OT config. the PWM sigPWM frequency nal Either during D: fSCF off time or ON Enabled time of the Z: fSCF PWM signal During ON time of the PWM signal During ON time of the PWM signal Window and Event Filters Behaviour of the output PWM "Before D" behaviour, "between D and Z" behaviour and "after Z" behaviour "Before D" behaviour, "between D and Z" behaviour and "after Z" behaviour "Before D" behaviour, "between D and Z" behaviour and "after Z" behaviour "Before D" behaviour, "between D and Z" behaviour and "after Z" behaviour
D Window Filter DWF[3:0] after C event
D Event Filter DEF[3:0] after DWF
Z Event Filter ZEF[3:0] after ZWF
0
0
000
Sensors not used
Z Window Filter ZWF[3:0] after D event
0
1
000
Sensors not used
0
0
D: fSCF Not Sensors equal to Enabled Z: SA&OT config. not used 000 PWM frequency Not Sensors equal to Enabled not used 000 Position OS1 disSensors abled used D: fSCF Z: fSCF
0
1
1
x
xxx
Z: fSCF
Either during OFF time or No filter in Sensor "Before Z" behaviour ON time of the mode and "after Z" behaviour PWM signal
Note: For fSCF selection, see Table 83
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See Table 30 on page 148
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 85. Functional Diagram of Z Detection after D Event
DS or DH
Begin
Z Window Filter turned on
ZWF[3:0] bits in MZFR register Switch Sampling Clock[D] -> Sampling Clock[Z]
Side change on Output PWM ? Yes
No
Change the side according to OS[2:0]
Wait for next sampling clock edge
Read enable by REO ? Yes
No
Filter off ? Yes Read enabled
No
End
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MOTOR CONTROLLER (Cont'd) 9.6.6.11 Speed Sensor Mode This mode is entered whenever the Tacho Edge Selection bits in the MPAR register are not both reset (TES[1:0] = 10, 01, 11). The corresponding block diagram is shown in Figure 86. Either Incremental Encoder or Tachogeneratortype speed sensor can be selected with the IS[1:0] bits in the MPHST register. 9.6.6.12 Tachogenerator Mode (IS[1:0] = 00, 01 or 10) Any of the MCIx input pins can be used as a tachogenerator input, with a digital signal (externally amplified for instance); the two remaining pins can be used as standard I/O ports. A digital multiplexer connects the chosen MCIx input to an edge detection block. Input selection is done with the IS[1:0] bits in the MPHST register. An edge selection block is used to select one of three ways to trigger capture events: rising edge, falling edge or both rising and falling edge sensi-
tive; set-up is done with the TES[1:0] bits (keeping in mind that TES[1:0] = 00 configuration is reserved for Position Sensor / Sensorless Modes). Having only one edge selected eliminates any incoming signal dissymmetry, which may due to pole-to-pole magnet dissymmetry or from a comparator threshold with low level signals. Figure 87 presents the signals generated internally with different tacho input and TES bit settings. Note on Hall Sensors: This configuration is also suitable for motors using 3 hall sensors for position detection and not driven in six-step mode (refer to "Speed Measurement Mode" on page 176). Note on initializing the Input Stage: As the IS[1:0] bits in the MPHST register are preload bits (new values taken into account at C event), the initialization value of the IS[1:0] bits has to be entered in Direct Access mode. This is done by setting the DAC bit in the MCRA register during the speed sensor input initialization routine.
Figure 86. Input Stage in Speed Sensor Mode (TES[1:0] bits = 01, 10, 11)
Input Block Input Comparator Block Event Detection Encoder Clock Direction
In1 Incremental In2
Clk D
Encoder interface
MPHST Register Inputn Sel Tacho or Encoder Tacho or Encoder Tacho or Free I/O MCIA 00 MCIB 01 MCIC
or or
IS[1:0]
MPAR Register
EDIR bit MCRC Register
TES[1:0] Tacho Capture
10
= According to IS[1:0] bits setting
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MOTOR CONTROLLER (Cont'd) 9.6.6.13 Encoder Mode (IS[1:0] = 11) Figure 88 shows the signals delivered by a standard digital incremental encoder and associated information: - Two 90 phased square signals with variable frequency proportional to the speed; they must be connected to MCIA and MCIB input pins, - Clock derived from incoming signal edges, - Direction information determined by the relative phase shift of input signals ( + or -90).
The Incremental Encoder Interface block aims at extracting these signals. As input logic is both rising and falling edge sensitive (independently from TES[1:0] bits setting), resulting clock frequency is four times the one of the input signals, thus increasing resolution for measurements. It may be noticed that Direction bit (EDIR bit in MCRC register) is read only and that it does'nt affect counting direction of clocked timer (cf Section ). As a result, one cannot extract position information from encoder inputs during speed reversal.
Figure 87. Tacho Capture events configured by the TES[1:0] bits Tacho input
TES[1:0]=11
Tacho Capture
TES[1:0]=01 TES[1:0]=10
Figure 88. Incremental Encoder output signals and derived information
MCIA Encoder inputs MCIB
Encoder Clock
Direction (EDIR bit) Sampling of MCIA to determine direction
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MOTOR CONTROLLER (Cont'd) Note If only one encoder output is available, it may be input either on MCIA or MCIB and an encoder clock signal will still be generated (in this case the frequency will be 50% less than with two inputs. The state of EDIR bit will depend on signals present on MCIA and MCIB pins, the result will be Table 35. Input Detection Block set-up
Input Detection Block Mode Sensor Type Edge sensitivity SR bit 1 TES[1:0] bits (Tacho Edge Selection) 00 IS[1:0] bits (Input Selection) 00 01 10 00 01 10 11 00 01 10 00 01 10 00 01 10
given by the sampling of MCIA with MCIB falling edges. 9.6.6.14 Summary Input Detection block set-up for the different available modes is summarized in the Table 35.
Position Sensor
Hall, Optical,...
Both rising and falling edges
Sensorless
N/A
N/A
0
00 Any configuration different from 00: 01 10 11 01
Incremental Encoder
Both rising and falling edges (imposed)
Rising edge Speed Sensor Tachogenerator, Hall, Optical... Falling edge x
10
Both rising and falling edges
11
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MOTOR CONTROLLER (Cont'd) Note on using the 3 MCIx pins as standard I/Os: When none of the MCIx pins are needed in the application (for instance when driving an induction motor in open loop), they can be used as standard I/O ports, by configuring the Motor ConTable 36. MCIx pin configuration summary
PCN TES SR IS[1:0] 00 01 10 11 00 01 10 11 xx 00 01 10 11 1 00 01 10 11 Digital Input Standard I/O Standard I/O Speed Sensor Standard I/O Digital Input Standard I/O Tachogenerator Standard I/O Standard I/O Digital Input Speed Sensor Digital Input Digital Input Standard I/O Encoder MCIA Analog Input Hi-Z or GND Hi-Z or GND NA Digital Input Standard I/O Standard I/O NA NA Analog Input Standard I/O MCIB Hi-Z or GND Analog Input Hi-Z or GND NA Standard I/O Digital Input Standard I/O NA NA Standard I/O Analog Input MCIC Hi-Z or GND Hi-Z or GND Analog input NA Standard I/O Standard I/O Digital Input NA NA Standard I/O Standard I/O Input Detection Block Mode Sensorless NA Position Sensor NA NA NA Phase comparator is ON. The IS[1:0] bits must not be modified to avoid spurious event detection in Motor Controller All MCIx pins are standard I/Os. Recommended configuration: phase comparator OFF From 1 to 3 MCIx pins reserved depending on sensor Comments
troller as follows: PCN=1, TES0 and IS=11. This disables the MCIx alternate functions and switches off the phase comparator. The state of the MCIx pins is summarized in Table 36.
0 00 1 0
All MCIx pins are reserved for the MTC peripheral
0
x
00
x
Standard I/O Standard I/O Analog Input Standard I/O Standard I/O Standard I/O NA
00
x
*When PCN=0, TES=0 SR=0, inputs in OFF-state are put in HiZ or grounded depending on the value of the DISS bit in the MSCR register.
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MOTOR CONTROLLER (Cont'd) 9.6.7 Delay Manager Figure 89. Overview of MTIM Timer in Switched and Autoswitched Mode
Tratio ck 8-bit Up Counter MTIM 8 ZH MZREG [Zn] Z H / ZS DH MDREG [Dn]
clr
1 0
MCRA register SWA bit
Z C
Compare MCRC register SZ bit
Compare MCRB register SDM* bit Filter /C MDFR register DWF[3:0] DS CH,S DS,H To interrupt generator To interrupt generator To interrupt generator
Filter /D MZFR register ZWF[3:0] ZS
MZPRV [Zn-1]
MCOMP [Cn+1]
ZH,S
Compare MCRC register SC bit = Register updated on R event
CH / CS
This part of the MTC contains all the time-related functions, its architecture is based on an 8-bit shift left/shift right timer shown in Figure 89. The MTIM timer includes: - An auto-updated prescaler - A capture/compare register for simulated demagnetization simulation (MDREG) - Two cascaded capture and one compare registers (MZREG and MZPRV) for storing the times between two consecutive BEMF zero crossings (ZH events) and for zero-crossing event simulation (ZS) - An 8x8 bit multiplier for auto computing the next commutation time - One compare register for phase commutation generation (MCOMP)
The MTIM timer module can work in two main modes when driving synchronous motors in sixsteps mode. In switched mode the user must process the step duration and commutation time by software. In autoswitched mode the commutation action is performed automatically depending on the rotor position information and register contents. This is called the hardware commutation event CH. When enabled by the SC bit in the MCRC register, commutation can also be simulated by writing a value directly in the MCOMP register that is compared with the MTIM value. This is called simulated commutation C S (See "Built-in Checks and Controls for simulated events" on page 171.). Both in switched mode and autoswitched mode , if the SC bit in the MCRC register is set (software commutation enabled), no comparison between
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MOTOR CONTROLLER (Cont'd) the MCOMP and MTIM register is enabled before a write access in the MCOMP register. This means that if the SC bit is set and no write access is done after in the MCOMP register, no CS commutation event will occur. In Speed Measurement mode, when using encoder or tachogenerator speed sensors (i.e. both TES[1:0] bits in the MPAR register are not reset and the input detection block is set-up to process sensor signals), motor speed can be measured but it is not possible drive a motor in six-step mode, either sensored or sensorless. Speed Measurement mode is useful for motors supplied with 3-phase sinewave-modulated PWM signals: - AC induction motors, - Permanent Magnet AC (PMAC) motors (although it needs three position sensors, they can be handled just like tachogenerator signals). This mode uses only part of the Delay Manager's resources. For more details refer to "Speed Measurement Mode" on page 176. Table 37. Switched and Autoswitched modes SWA bit
0 1
Commutation Type
Switched mode Autoswitched mode
MCOMP User access
Read/Write Read/Write
9.6.7.1 Switched Mode This feature allows the motor to be run step-bystep. This is useful when the rotor speed is still too low to generate a BEMF. It can also run other kinds of motor without BEMF generation such as induction motors or switch reluctance motors. This mode can also be used for autoswitching with all computation for the next commutation time done by software (hardware multiplier not used) and using the powerful interrupt set of the peripheral. In this mode, the step time is directly written by software in the commutation compare register Table 38. Step Update
Mode x Switched Autoswitched Speed measure TES[1:0] xx 00 00 01 10 11 CKE SWA Clock bit bit State 0 x Disabled 1 1 1 0 1 x Enabled Enabled Enabled Read
MCOMP. When the MTIM timer reaches this value a commutation occurs (C event) and the MTIM timer is reset. At this time all registers with a preload function are loaded (registers marked with (*) in Section 9.6.13). The CI bit of MISR is set and if the CIM bit in the MISR register is set an interrupt is generated. The MTIM timer prescaler (Step ratio bits ST[3:0] in the MPRSR register) is user programmable. Access to this register is not allowed while the MTIM timer is running (access is possible only before the starting the timer by means of the CKE bit) but the prescaler contents can be incremented/decremented at the next commutation event by setting the RMI (decrement) or RPI (increment) bits in the MISR register. When this method is used, at the next commutation event the prescaler value will be updated but also all the MTIM timer-related registers will be shifted in the appropriate direction to keep their value. After it has been taken into account, (at commutation) the RPI or RMI bit is reset by hardware. See Table 38. Only one update per step is allowed, so if both RPI and RMI bits are set together by software, this does not affect the MISR register: the write access to these two bits together is not taken into account and the previous state is kept. This means that if either RPI or RMI bit was set before the write access of both bits at the same time, this bit (RPI or RMI) is kept at 1. If none of them was set before the simultaneous write access, none of them will be set after the write access. In switched mode, BEMF and demagnetization detection are already possible in order to pass in autoswitched mode as soon as possible but Z and D events do not affect the timer contents. In this mode, if an MTIM overflow occurs, it restarts counting from 0x00h and the OI overflow flag in the MCRC register is set if the TES[1:0] bits = 00. Caution: In this mode, MCOMP must never be written to 0.
Ratio Increment Ratio Decrement (Slow Down) (Speed-Up) Write the ST[3:0] value directly in the MPRSR register Set RPI bit in the MISR reg- Set RMI bit in the MISR regAlways ister till next commutation ister till next commutation possible Automatically updated according to MZREG value
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MOTOR CONTROLLER (Cont'd) Figure 90. Step Ratio Functional Diagram
fPERIPH R+ +1 MPRSR Register MTIM Timer = 100h? 4 1 / 2Ratio Zn < 55h? RTratio ck 2 MHz - 62.5 Hz MTIM Timer control over Tratio and register operation 1/2
ST[3:0] Bits
-1
MTIM Timer Overflow
Z Capture with MTIM Timer Underflow (Zn < 55h)
Begin
Begin
Ratio < Fh?
No
Ratio > 0?
No
Yes Ratio = Ratio + 1 MZREG = MZREG / 2 MZPRV = MZPRV/2 MDREG = MDREG/2 MCOMP = MCOMP/2** Counter = Counter/2
Yes Ratio = Ratio - 1 MZREG = MZREG x 2 MZPRV = MZPRV x 2 MDREG = MDREG x 2 Counter = Counter x 2 Compute MCOMP
End
End
Slow-down control
** Only in Auto-switched mode (SWA=1 in MCRA register)
Speed-up control
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MOTOR CONTROLLER (Cont'd) 9.6.7.2 Autoswitched Mode In this mode, using the hardware commutation event CH (SC bit reset in MCRC register), the MCOMP register content is automatically computed in real time as described below and in Figure 91. The C (either C S or CH) event has no effect on the contents of the MTIM timer. When a ZH event occurs the MTIM timer value is captured in the MZREG register, the previous captured value is shifted into the MZPRV register and the MTIM timer is reset. See Figure 71. When a ZS event occurs, the value written in the MZREG register is shifted into the MZPRV register and the MTIM timer is reset. One of these two registers, (when the SC bit = 0 in the MCRC register and depending on the DCB bit in the MCRA register), is multiplied with the contents of the MWGHT register and divided by 256. The result is loaded in the MCOMP compare register, which automatically triggers the next hardware commutation (C H event). Note: The result of the 8*8 bit multiplication, once written in the MCOMP register is compared with the current MTIM value to check that the MCOMP value is not already less than the MTIM value due to the multiplication time. If MCOMP<=MTIM, a CH event is generated immediately and the MCOMP value is overwritten by the MTIM value. Table 39. Multiplier Result
DCB bit 0 1 Commutation Delay MCOMP = MWGHT x MZPRV / 256 MCOMP = MWGHT x MZREG / 256 MWGHT [an+1] 8 MCRA Register MCRC register A x B / 256 8
cur because no comparison will be done between MCOMP and MTIM. Therefore, it is recommended in autoswitched mode, when using software commutation feature (SC bit is set) and for a normal event sequence, the corresponding value to be put in MCOMP has to be written during the Z interrupt routine (because MTIM has just been reset), so that there is no spurious comparison. If the SC bit is set during a Z event interrupt, then , the result of the 8*8 bits hardware multiplication can be overwritten by software in the MCOMP register. When simulated commutation mode is enabled, the event sequence is no longer respected, meaning that the peripheral will accept consecutive commutation events and not necessarily wait for a D event after a Cs event. In this case the MCOMP register can be written immediately after the previous C event, in the C interrupt service routine for example. Figure 91. C H Processor Block
MZREG [Zn] ZH/ZS MZPRV [Zn-1] MCRA Register DCB bit n-1 n
After each shift operation the multiply is recomputed for greater precision. Using either the MZREG or MZPRV register depends on the motor symmetry and type. The MWGHT register gives directly the phase shift between the motor driven voltage and the BEMF. This parameter generally depends on the motor and on the speed. Setting the SC bit in the MCRC register enables the simulated commutation event (C S) generation. This means that a write access is possible to the MCOMP register and the MTIM value will be compared directly with the value written by software in the MCOMP register to generate the CS event. The comparison is enabled as soon as a write access is done to the MCOMP register. This means that if the SC bit is set and no write access is done to the MCOMP register, the C event will never oc-
SWA bit =1 & SC bit =0
MCOMP [Cn+1]
8
= Register updated on R event
Note 1: An overflow of the MTIM timer generates an RPI interrupt if the RIM bit is set. Note 2: When simulated commutation mode is enabled, the D and Z event are not ignored by the peripheral, this means that if a Z event happens, the MTIM 8 bit internal counter will be reset. Caution: MCOMP must never be written to 0 for a CS event generation.
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MOTOR CONTROLLER (Cont'd) Auto-updated Step Ratio Register: a) In switched mode: the MTIM timer is driven by software only and any prescaler change has to be done by software (see page 165 for more details). b) In autoswitched mode: an auto-updated prescaler always configures the MTIM timer for best accuracy. Figure 90 shows the process of updating the Step Ratio bits: - When the MTIM timer value reaches FFh, the prescaler is automatically incremented in order to slow down the MTIM timer and avoid an overflow. To keep consistent values, the MTIM register and all the relevant registers are shifted right (divided by two). The RPI bit in the MISR register is set and an interrupt is generated (if RIM is set). The timer restarts counting from its median value 0x80h and if the TES[1:0] bits = 00, the OI bit in the MCRC register is set. - When a Z-event occurs, if the MTIM timer value is below 55h, the prescaler is automatically decremented in order to speed up the MTIM timer and keep precision better than 1.2%. The MTIM register and all the relevant registers are shifted left (multiplied by two). The RMI bit in the MISR register is set and an interrupt is generated if RIM is set. - If the prescaler contents reach the value 0, it can no longer be automatically decremented, the MTC continues working with the same prescaler value, i.e. with a lower accuracy. No RMI interrrupt can be generated. - If the prescaler contents reach the value 15, it can no longer be automatically incremented. When the timer reaches the value FFh, the prescaler and all the relevant registers remain unchanged and no interrupt is generated, the timer restarts counting from 0x00h and if the TES[1:0]
bits = 00, the OI bit in the MCRC register is set at each overflow (it has to be reset by software). The RPI bit is no longer set. The PWM is still generated and the D and Z detection circuitry still work, enabling the capture of the maximum timer value. The automatically updated registers are: MTIM, MZREG, MZPRV, MCOMP and MDREG. Access to these registers is summarized in Table 41. 9.6.7.3 Debug Option In both Switched Mode and Autoswitched Mode, setting the bit DG in MPWME register enables the Debug Option. This option consists of outputting the C, D and Z signals in real time on pins MCZEM and MCDEM. This is very useful during the debug phase of the application. Figure 92 shows the signals output on pins MCDEM and MCZEM with the debug option. Note 1: When the delay coefficient equals 0/256 (C event immediately after Z event), a glitch appears on MCZEM pin to be able to see the event even in this case. This option is also available in Speed measurement mode with different signal outputs (see Figure 92): - MCDEM toggles when a capture event is generated, - MCZEM toggles every time a U event is generated. These signals are only available if the TES[1:0] bits = 10, 01 or 11. Note 2: In sensor mode, the MCDEM output pin toggles at each C event. The MCZEM pin outputs the Z event.
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MOTOR CONTROLLER (Cont'd) Figure 92. Output on pins MCDEM and MCZEM with debug option (DG bit=1)
MCDEM
MCZEM C D Z C C Z D Z C
D
Debug outputs in Sensorless mode
MCDEM
MCZEM C Z C Z C Z C Z C Z
Debug outputs in Sensor mode
MCDEM C C C C C C C C C C
MCZEM
U events
Debug outputs in Speed Measurement mode (TES[1:0] bits equal to 00, 01, 10).
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MOTOR CONTROLLER (Cont'd) Note on using the auto-updated MTIM timer: The auto-updated MTIM timer works accurately within its operating range but some care has to be taken when processing timer-dependent data such as the step duration for regulation or demagnetization. For example if an overflow occurs when calculating a simulated end of demagnetization (MCOMP+demagnetisation_time>FFh), the value that is stored in MDREG will be: 80h+(MCOMP+demagnetization_time-FFh)/2. Note on commutation interrupts: It is good practice to modify the configuration for the next step as soon as possible, i.e within the commutation interrupt routine. All registers that need to be changed at each step have a preload register that enables the modifications for a complete new configuration to be performed at the same time (at C event in normal mode or when writing the MPHST register in direct access mode).
These configuration bits are: CPB, HDM, SDM and OS2 in the MCRB register and IS[1:0], OO[5:0] in the MPHST register. Note on initializing the MTC: As shown in Table 41 all the MTIM timer registers are in read-write mode until the MTC clock is enabled (with the CKE bit). This allows the timer, prescaler and compare registers to be properly initialized for start-up. In sensorless mode, the motor has to be started in switched mode until a BEMF voltage is present on the inputs. This means the prescaler ST[3:0] bits and MCOMP register have to be modified by software. When running the ST[3:0] bits can only be incremented / decremented, so the initial value is very important. When starting directly in autoswitched mode (in sensor mode for example), write an appropriate value in the MZREG and MZPRV register to perform a step calculation as soon as the clock is enabled.
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MOTOR CONTROLLER (Cont'd) 9.6.7.4 Built-in Checks and Controls for simulated events As described in Figure 89. on page 164, MZREG, MDREG and MCOMP registers are capture/compare registers. The Compare registers are write accessible and can be used to generate simulated events. The value of the MTIM timer is compared with the value written in the registers and when the MTIM value reaches the corresponding register value, the simulated event is generated. Simulated event generation is enabled when the corresponding bits are set: - In the MCRB register for simulated demagnetisation - SDM for simulated demagnetisation - In the MCRC register for simulated zero-crossing and commutation. - SC for simulated commutation - SZ for simulated zero-crossing event. To avoid a system stop, special attention is needed when writing in the register to generate the corresponding simulated event. The value written in
the register has to be greater than the current value of the MTIM timer when writing in the registers. If the value written in the registers (MDREG, MZREG or MCOMP) is already less than the current value of MTIM, the simulated event will never be generated and the system will be stopped. For this reason, built-in checks and controls have been implemented in the MTIM timer. If the value written in one of those registers in simulated event generation mode is less than or equal to the current value of the timer when it is compared, the simulated event is generated immediately and the value of the MTIM timer at the time the simulated event occurs overwrites the value in the registers. Like that the value in the register really corresponds to the simulated event generation and can be re-used to generate the next simulated event. So, the value written in the registers able to generate simulated events is checked by hardware and compare to the current MTIM value to verify that it is greater.
Figure 93. Simulated demagnetisation / zero-crossing event generation (SC=0)
After C interrupt MDREG value checked if MDREG<=MTIM Immediate DS generation ZH ZH After D interrupt MZREG value checked if MZREG<=MTIM Immediate ZS generation ZS
ZS
MTIM Timer Value
DS
DH
DS
CH
CH
CH
During C interrupt Simulated or Hardware D/Z events Value written in MDREG/MZREG if simulated event generation
Z S Simulated zero-crossing DS Simulated demagnetisation Z H Hardware zero-crossing CH Hardware commutation
t
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MOTOR CONTROLLER (Cont'd) When using hardware commutation CH, the sequence of events needed is C H then D and finally Z events and the value written in the registers are checked at different times. If SDM bit is set, meaning simulated demagnetisation, a value must be written in the MDREG register to generate the simulated demagnetisation. This value must be written after the C (either Cs or CH) event preceding the simulated demagnetisation. If SZ bit is set, meaning simulated zero-crossing event, a value must be written in the MZREG register to generate the simulated zero-crossing. This value must be written after the D event (DH or DS) preceding the simulated zero-crossing. When using simulated commutation (CS), the result of the 8*8 hardware multiplication of the delay manager is not taken in account and must be overwritten if the SC bit has been set in a Z event interrupt and the sequence of events is broken meaning that several consecutive simulated commutations can be implemented. As soon as the SC bit is set in the MCRC register, the system won't necessarily expect a D event after a C event. This can be used for an application in sensor mode with only one Hall Effect sensor for example. Be careful that the D and Z events are not ignored by the peripheral, this means that for example if a
Z event occurs, the MTIM timer is reset. In Simulated Commutation mode, the sequence D -> Z is expected, and this order must be repected. As the sequence of events may not be the same when using simulated commutation, as soon as the SC bit is set, the capture/compare feature and protection on MCOMP register is reestablished only after a write to the MCOMP register. This means that as soon as the SC bit is set, if no write access is done to the MCOMP register, no commutation event will be generated, whatever the value of MCOMP compared to MTIM at the time SC is set. This does not depend on the running mode: switched or autoswitched mode (SWA bit). If software commutation event is used with a normal sequence of events C-->D-->Z, it is recommended to write the MCOMP register during the Z interrupt routine to avoid any spurious comparison as several consecutive Cs events can be generated. Note that two different simulated events can be used in the same step (like DS followed by ZS). Note also that for more precision, it is recommended to use the value captured from the preceding hardware event to compute the value used to generate simulated events. Figure 93, Figure 94 and Figure 95 shows details of simulated event generation.
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MOTOR CONTROLLER (Cont'd) Figure 94. Simulated commutation event generation with only 1 Hall effect sensor (SC bit =1)
After C interrupt MCOMP is written for Cs event if MCOMP<=MTIM Immediate CS generation Z C interrupt SC reset in MCRB Next C event = C H with 8*8 bit multiplication Z Z
MTIM Timer Value
D CS CS CH
D CS CS CH
C interrupt SC set in MCRC
Z zero-crossing event D Demagnetisation event CH Hardware commutation CS Simulated commutation
Note: If the SC bit is set during Z event interrupt, then the 8*8 bit hardware multiplication result can be overwritten in the MCOMP register. Otherwise, Figure 95. Simulated commutation and Z event
SC bit is reset the result of the hardware multiplication is put in MCOMP-->CH and compared with MTIM once written Z
t when the SC bit is set, the result of the multiplication is not taken into account after a Z event.
SC bit is set during Z IT the hardware multiplication is taken into account but the value in MCOMP can be overwritten Z Z
SC bit is already set when Z IT occurs. The hardware multipli-cation is not taken into account A value has to be written in the MCOMP register Z
MTIM Timer Value
D D D
CH
Cs
Cs
MCOMP register
Z zero-crossing event D Demagnetisation event CH Hardware commutation CS Simulated commutation
t
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MOTOR CONTROLLER (Cont'd) The Figure 96 gives the step ratio register value (left axis) and the number of BEMF sampling during one electrical step with the corresponding accuracy on the measure (right axis) as a function of the mechanical frequency. For a given prescaler value (step ratio register) the mechanical frequency can vary between two fixed values shown on the graph as the segment ends. In autoswitched mode, this register is automatically incremented/decremented when the step frequency goes out of this segment.
At fcpu=4MHz, the range covered by the Step Ratio mechanism goes from 2.39 to 235000 (pole pair x rpm) with a minimum accuracy of 1.2% on the step period. To read the number of samples for Zn within one step (right Y axis), select the mechanical frequency on the X axis and the sampling frequency curve used for BEMF detection (PWM frequency or measurement window frequency). For example, for N.Frpm = 15,000 and a sampling frequency of 20kHz, there are approximately 10 samples in one step and there is a 10% error rate on the measurement.
Figure 96. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate
avg Zn ~ 55h 1.2%
ST[3:0] Step Ratio (Decimal) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
avg Zn ~ FFh 0.4% Fn avg Zn ~ 7Fh 0.6% 3.Fn avg Zn ~ 55h 1.2% Fn+1 = 2.Fn
avg Zn ~ 7Fh 0.6% avg Zn ~ FFh 0.4%
BEMF samples
Zn/Zn
1 100%
200 Hz 20 kHz
3.Fn+1 = 6.Fn
2
50%
4
10
10% 0%
N.Frpm
1 2.39 4.79 7.18 9.57 14.4 19.1 28.7 38.3 57.4 76.6 115 9800 14700 19600 29400 39200 58800 78400 118000 153 230 306 460 614 920 1230 1840 2450 3680 4900 7350 157000 235000
Fstep = 6.N.Frpm = N.F / 10 N.F = 10.Fstep
Fstep: Electrical step frequency N: Pole pair number
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MOTOR CONTROLLER (Cont'd) Table 40. Step Frequency/Period Range (4MHz)
Step Ratio Bits ST[3:0] in MPRSR Register 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Maximum Step Frequency 23.5 kHz 11.7 kHz 5.88 kHz 2.94 kHz 1.47 kHz 735 Hz 367 Hz 183 Hz 91.9 Hz 45.9 Hz 22.9 Hz 11.4 Hz 5.74 Hz 2.87 Hz 1.43 Hz 0.718 Hz Minimum Step Frequency 7.85 kHz 3.93 kHz 1.96 kHz 980 Hz 490 Hz 245 Hz 123 Hz 61.3 Hz 30.7 Hz 15.4 Hz 7.66 Hz 3.83 Hz 1.92 Hz 0.958 Hz 0.479 Hz 0.240 Hz Minimum Step Period 42.5 s 85 s 170 s 340 s 680 s 1.36 ms 2.72 ms 5.44 ms 10.9 ms 21.8 ms 43.6 ms 87 ms 174 ms 349 ms 697 ms 1.40 s Maximum Step Period 127.5 s 255 s 510 s 1.02 ms 2.04 ms 4.08 ms 8.16 ms 16.32 ms 32.6 ms 65.2 ms 130 ms 261 ms 522 ms 1.04 s 2.08 s 4.17 s
Table 41. Modes of Accessing MTIM Timer-Related Registers
State of MCRA / MCRB / MPAR Register Bits RST bit 0 TES[1:0] SWA bit CKE bit xx x 0 Mode Configuration Mode Access to MTIM Timer Related Registers Read Only Read / Write Access Access MTIM, MTIML, MZPRV, MZREG, MCOMP, MDREG, ST[3:0] MCOMP, MDREG, MZREG, MZPRV RMI bit of MISR: 0: No action 1: Decrement ST[3:0]
0
00
0
1
Switched Mode
MTIM, ST[3:0]
0
00
1
1
01 0 10 11 x 1
RPI bit of MISR: 0: No action 1: Increment ST[3:0] MDREG, MCOMP, MZREG, MZPRV, RMI, RPI bit of MISR: Autoswitched Mode MTIM, ST[3:0] Set by hardware, (increment ST[3:0]) Cleared by software MDREG,MZREG, MZPRV, MTIM, MTIML, RMI, RPI bit of MISR, : Speed Sensor Mode ST[3:0] Set by hardware, (increment or decrement ST[3:0]), cleared by software.
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MOTOR CONTROLLER (Cont'd) 9.6.7.5 Speed Measurement Mode Motor speed can be measured using two methods depending on sensor type: period measurement or pulse counting. Typical sensor handling is described here. Incremental encoders allows accurate speed measurement by providing a large number of pulses per revolution (ppr) with ppr rates up to several thousands; the higher the ppr rate, the higher the resolution. The proposed method consists of
counting the number of clock cycles issued by the Incremental Encoder Interface (Encoder Clock) during a fixed time window (refer to Figure 98). The tachogenerator has a much lower ppr rate than the encoder (typically factor 10). In this context, it is more meaningful to measure the period between Tacho Captures (i.e. relevant transitions of the incoming signals). Accuracy is imposed by the reference clock, i.e. the CPU clock (refer to Figure 97).
Figure 97. Tachogenerator period acquisition using MTIM timer
Decreasing Speed
Comparator Output Tacho Capture Compare Value MTIM Counter Value
S
Interrupts
C C
C
C S
C
C
C
C
To interrupt generator (Capture Event)
To interrupt generator (Speed Error Event)
Figure 98. Encoder Clock frequency measure using MTIM timer
Decreasing Speed
Encoder Clock Capture (triggered by software or Real Time Clock)
MTIM Counter Value
Interrupts
C C To interrupt generator (Capture Event)
C
C
C
C
C
C
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MOTOR CONTROLLER (Cont'd) Hall sensors (or equivalent sensors providing position information) are widely used for motor control. There are two cases to be considered: - BLDC motor or six-step synchronous motor drive; "Sensor Mode" is recommended in this case, as most tasks are performed by hardware in the Delay Manager - BLAC, asynchronous or motors supplied with 3phase sinewave-modulated PWM signals in general; in this case "Speed Sensor Mode" allows high accuracy speed measurement (the Sensor Mode of the Delay Manager being unsuitable for sinewave generation). Position information is handled by software to lock the statoric field to the rotoric one for driving synchronous motors. Hall sensors are usually arranged in a 120 configuration. In that case they provide 3 ppr with both rising and falling edge triggering; the tachogenerator measurement method can therefore be applied. The main difference lies in the fact that one must use the position information they provide. This can be done using the three MCIx pins and the analog multiplexer to know which of the 3 sensors toggled; an interrupt is generated just after the expected transition (refer to Figure 99). As described in Figure 100, the MTIM Timer is reconfigured depending on the selected sensor. This means that most of Delay Manager registers are used for a different purpose, with modified functionalities. For greater precision, the MTIM Up-counter is extended to 16 bits using MTIM and an additional MTIML register. On a capture event, the current counter value is captured and the counter
[MTIM:MTIML] is cleared. The counting direction is not affected by the EDIR bit when using an encoder sensor. A 16-bit capture register is used to store the captured value of the extended MTIM counter: the speed result will be either a period in clock cycles or a number of encoder pulses. This 16-bit register is mapped in the MZREG and MZPRV register addresses. To ensure that the read value is not corrupted between the high and low byte accesses, a read access to the MSB of this register (MZREG) locks the LSB (ie MZPRV content is locked) until it is read and any other capture event in between these two accesses is discarded. A compare unit allows a maximum value to be entered for the tacho periods. If the 16-bit counter [MTIM:MTIML] exceeds this value, a Speed Error interrupt is generated. This may be used to warn the user that the tachogenerator signal is lost (wires disconnected, motor stalled,...). As 8-bit accuracy is sufficient for this purpose, only the MSByte of the counter (i.e. MTIM) is compared to 8-bit compare register, mapped in the MDREG register location. The LSByte is nevertheless compared with a fixed FFh value. Available values for comparison are therefore FFFFh, FEFFh, FDFFh, ..., 01FFh, 00FFh. Note: This functionality is not useful when using an encoder. With an encoder, user must monitor the captured values by software during the periodic capture interrupts: for instance, when driving an AC motor, if the values are too low compared to the stator frequency, a software interrupt may be triggered.
Figure 99. Hall sensor period acquisition using MTIM timer
1 mechanical cycle
MCIA: Hall Sensor 1 MCIB: Hall Sensor 2 MCIC: Hall Sensor 3 Period measurements 1-2 Tacho Capture Interrupts 2-3 3-1 1-2 2-3 3-1
C
C
C
C
C
C
C
C
C
C
C
C
C
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MOTOR CONTROLLER (Cont'd) Figure 100. Overview of MTIM Timer in Speed Measurement Mode
Registers: MZFR* MPHST* MPAR* Bits: Tacho Capture MTIM Read access RTC interrupt RPI +1 MPRSR Register MTIM Register = FFh? 4 1 / 2Ratio Tratio -1 RMI 16 MHz - 500 Hz Clock MTIM MSbits C C 16-bit Up Counter MTIML LSbits
clr C
ECM IS[1:0] TES[1:0] MPAR* and MPHST* Registers C IS[1:0] bits TES[1:0] bits
fMTC fPERIPH (16MHz) (4MHz) Encoder Clock
ST[3:0] Bits
MZREG < 55h?
MZREG
16-bit Capture Register
MZPRV
MDREG
FFh (Fixed)
Compare
Compare
S Notes:
*
= Register updated on R event = Register set-up described in Speed Sensor Mode Section
C S
To interrupt generator (Capture Event) To interrupt generator (Speed Error Event)
RPI RMI
To interrupt generator (Ratio Increment Event) To interrupt generator (Ratio Decrement Event)
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) A logic block manages capture operations depending on the sensor type. A capture is initiated on an active edge ("Tacho capture" event) when using a tachogenerator. If an encoder is used, the capture is triggered on two events depending on the Encoder Capture Mode bit (ECM) in the MZFR register: - Reading the MSB of the counter in manual mode (ECM = 1) - Interrupt from the Real Time Clock in automatic mode (ECM = 0) The clock source of the counter is selected depending on sensor type: - Motor Control Peripheral clock (16 MHz) with tachogenerator or Hall sensors - Encoder Clock In order to optimize the accuracy of the measurement for a wide speed range, the auto-updated prescaler functionality is used with slight modifications compared to Sensor/Sensorless Modes (refer to Figure 101 and Table 38). - When the [MTIM:MTIML] timer value reaches FFFFh, the prescaler is automatically incremented in order to slow down the counter and avoid an overflow. To keep consistent values, the MTIM and MTIML registers are shifted right (di-
vided by two). The RPI bit in the MISR register is set and an interrupt is generated (if RIM is set). - When a capture event occurs, if the [MTIM:MTIML] timer value is below 5500h, the prescaler is automatically decremented in order to speed up the counter and keep precision better than 0.005% (1/5500h). The MTIM and MTIML registers are shifted left (multiplied by two). The RMI bit in the MISR register is set and an interrupt is generated if RIM is set. - If the prescaler contents reach the value 0, it can no longer be automatically decremented, the [MTIM:MTIML] timer continues working with the same prescaler value, i.e. with a lower accuracy. No RMI interrrupt can be generated. - If the prescaler contents reach the value 15, it can no longer be automatically incremented. When the timer reaches the value FFFFh, the prescaler and all the relevant registers remain unchanged and no interrupt is generated, the timer clock is disabled, and its contents stay at FFFFh. The capture logic block still works, enabling the capture of the maximum timer value. The only automatically updated registers for the Speed Sensor Mode are MTIM and MTIML. Access to Delay manager registers in Speed Sensor Mode is summarised in Table 41.
Figure 101. Auto-updated prescaler functional diagram
[MTIM:MTIML] Timer Overflow (MTIM = MTIML = FFh) Capture with [MTIM:MTIML] Timer < 5500h (MZREG < 55h)
Begin
Begin
No Ratio < Fh? Ratio > 0?
No
Yes Ratio = Ratio + 1 Counter = Counter/2
Yes Ratio = Ratio - 1 Counter = 0
End
End
Slow-down control
Speed-up control
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Three kinds of interrupt can be generated in Speed Sensor Mode, as summarized in Figure 102: - C interrupt, when a capture event occurs; this interrupt shares resources (Mask bit and Flag) with the Commutation event in Switched/Autoswitched Mode, as these modes are mutually exclusive. - RPI/RMI interrupts occur when the ST[3:0] bits of the MPSR register are changed, either automatically or by hardware. - S interrupt occurs when a Speed Error happens (i.e. a successful comparison between [MTIM:MTIML] and [MDREG:FF]). This interrupt has the same channel as the Emergency Stop interrupt (MCES), as it also warns the user about abnormal system operation. The respective Flag bits have to be tested in the interrupt service routine to differentiate Speed Errors from Emergency Stop events. These interrupts may be masked individually. Note on Delay Manager Initialization in Speed Figure 102. Prescaler auto-change example
CAPTURE
Measurement Mode: In order to set-up the [MTIM:MTIML] counter properly before any speed measurement, the following procedure must be applied: - The peripheral clock must be disabled (resetting the CKE bit in the MCRA register) to allow write access to ST[3:0], MTIM and MTIML (refer to Table 41), - MTIM, MTIML must be reset and appropriate values must be written in the ST[3:0] prescaler adapt to the frequency of the signal being measured and to allow speed measurement with sufficient resolution. Note on MTIML: The Least Significant Byte of the counter (MTIML) is not used when working in Position Sensor or Sensorless Modes. Debug option: a signal reflecting the capture events may be output on a standard I/O port for debugging purposes. Refer to section9.6.7.3 on page 168 for more details.
EVENTS
[MTIM:MTIML] FFFFh FAFFh
USUAL
WORKING RANGE
8000h 5500h
C S Notes:
C S RPI RMI Events: Capture Speed Error Ratio Increment Ratio Decrement
[MTIM:MTIML] Input Clock: Fx (ST[3:0] = n)
C RPI
C
C RMI
C
Fx / 2 (ST[3:0] = n+1)
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.7.6 Summary The use of the Delay manager registers for the various available modes is summarized in Table 42. Table 42. MTIM Timer-related Registers
Name MTIM MTIML MZREG MZPRV MCOMP MDREG Reset Value 00h 00h 00h 00h 00h 00h Switched / Auto Switched Mode Timer Value N/A Capture/compare Zn Capture Zn-1 Compare Cn+1 Demagnetization Dn Speed Measurement Mode 16-bit Timer MSB Value 16-bit Timer LSB Value Capture of 16-bit Timer MSB Capture of 16-bit Timer LSB N/A Compare for Speed Error interrupt generation
9.6.8 PWM Manager The PWM manager controls the motor via the six output channels in voltage mode or current mode depending on the V0C1 bit in the MCRA register. A block diagram of this part is given in Figure 104. 9.6.8.1 Voltage Mode In Voltage mode (V0C1 bit = "0"), the PWM signal which is applied to the switches is generated by the 12-bit PWM Generator compare U. Its duty cycle is programmed by software (refer to the PWM Generator section) as required by the application (speed regulation for example). The current comparator is used for safety purposes as a current limitation. For this feature, the detected current must be present on the MCCFI pin and the current limitation must be present on pin MCCREF. This current limitation is fixed by a volt-
age reference depending on the maximum current acceptable for the motor. This current limitation is generated with the VDD voltage by means of an external resistor divider but can also be adjusted with an external reference voltage ( 5 V). The external components are adjusted by the user depending on the application needs. In Voltage mode, it is mandatory to set a current limitation. As this limitation is set for safety purposes, an interrupt can be generated when the motor current feedback reaches the current limitation in voltage mode. This is the current limitation interrupt and it is enabled by setting the corresponding CLM bit in the MIMR register. This is useful in voltage mode for security purposes. The PWM signal is directed to the channel manager that connects it to the programmed outputs (see Figure 104).
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.8.2 Over Current Handling in Voltage mode When the current limitation interrupt is enabled by setting the CLIM bit in the MIMR register (available only in Voltage mode), the OCV bit in MCRB register will determine the effect of this interrupt on the MCOx outputs as shown in Table 43. Table 43. OCV bit effect
CLIM bit CLI bit OCV bit 0 0 1 1 0 1 0 1 x x x 0 Output effect Interrupt Normal running No mode PWM is put OFF on Current loop No effect Normal running No mode PWM is put OFF on Current loop Yes effect All MCOx outputs are put in reset Yes state (MOE reset)
The detected current input must be present on the MCCFI pin. 9.6.8.4 Current Feedback Comparator Two programmable filters are implemented: - A blanking window ( Current Window Filter) after PWM has been switched ON to avoid spurious PWM OFF states caused by parasitic noise - An event counter (Current Feedback Filter) to prevent PWM being turned OFF when the first comparator edge is detected. Figure 103. Current Window and Feedback Filters
PWM on
No
1
1
1
End of Blanking Window ?
CURRENT WINDOW FILTER
For safety purposes, it can be necessary to put all MCOx outputs in reset state (high impedance or low state depending on the DISS bit in the MSCR register) on a current limitation interrupt. This is the purpose of the OCV bit. When a current limitation interrupt occurs, if the OCV bit is reset, the effect on the MCOx outputs is only to put the PWM signal OFF on the concerned outputs. If the OCV bit is set, when the current limitation interrupt occurs, all the MCOx outputs are put in reset state. 9.6.8.3 Current Mode In current mode, the PWM output signal is generated by a combination of the output of the measurement window generator (see Figure 105) and the output of the current comparator, and is directed to the output channel manager as well (Figure 106). The current reference is provided to the comparator by Phase U, V or W of the PWM Generator (up to 12-bit accuracy) the signal from the three compare registers U, V or W can be output by setting the PWMU, PWMV or PWMW bits in the MPWME register. The PWM signal is filtered through an external RC filter on pin MCCREF.
Yes
CURRENT FEEDBACK FILTER
Yes
No
Current > Limit ?
Reset counter
No
Limit=1?
Increment counter
No
Yes Counter= Limit?
Yes Set the CL bit
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Table 44. Current Window filter Setting
CFW2 CFW1 CFW0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Blanking window length Blanking window off 0.5 s 1 s 1.5 s 2 s 2.5 s 3 s 3.5 s
Table 45. Current Feedback Filter Setting
CFF2 0 0 0 0 1 1 1 1 CFF1 0 0 1 1 0 0 1 1 CFF0 0 1 0 1 0 1 0 1 Nb of Feedback Samples needed to turn OFF PWM 1 2 3 4 5 6 7 8
Note: Times are indicated for 4 MHz fPERIPH The Current Window filter is activated each time the PWM is turned ON. It blanks the output of the current comparator during the time set by the CFW[2:0] bits in the MCFR register. The reset value is 000b (blanking window off). The Current feedback filter sets the number of consecutive valid samples (when current is above the limit) needed to generate the active CL event used to turn OFF the PWM. The reset value is 1. The sampling of the current comparator is done at fPERIPH/4.
The ON time of the resulting PWM starts at the end of the measurement window (rising edge), and ends either at the beginning of the next measurement window (falling edge), or when the current level is reached. Note: Be careful that the current comparator is OFF until the CKE and/or DAC bits are set in the MCRA register.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.8.5 Current feedback amplifier In both current and voltage mode, the current feedback from the motor can be amplified before entering the comparator. This is done by an integrated Op-amp that can be used when the OAON bit is set in the OACSR register and the CFAV bit in the MREF register is reset. This allows the three points of the Op-amp to be accessed for a programmable gain. The CFAV bit in the MREF register selects the MCCFI or OAZ pin as the comparator input as shown in the following table. Table 46. Comparator input selection
CFAV bit 0 1 Meaning Select OAZ as the current comparator input Select MCCCFI as the current comparator input
If the amplifier is not used for current feedback, it can be used for other purposes. In this case, the OAON bit in the OACSR register and the CFAV bit in the MREF register both have to be set. This means that the current feedback has to be on the Figure 104. Current Feedback
MREF Register PWME[U:V:W] bit MCPWMU/V/W
MCCFI pin to be directly connected to the comparator and the OAP, OAN and OAZ pins can be used to amplify another signal. Both the OAZ and MCCFI pins can be connected to an ADC entry. See (Figure 104). Note: The MCCFI pin is not available in TQFP32; SDIP32 and TQFP44 devices. In this case, the CFAV bit must be reset. The choice to use the Opamp or not is made with the OAON bit. 9.6.8.6 Measurement Window In current mode, the measurement window frequency can be programmed between 390Hz and 50KHz by the means of the SA[3:0] bits in the MPRSR register. Note: These frequencies are given for a 4 MHz peripheral input frequency for a BLDC drive (XT16, XT8 bits in MCONF register). In sensorless mode this measurement window can be used to detect BEMF zero crossing events. Its width can be defined between 2.5s and 40s as a minimum in sensorless mode by the OT[3:0] bits in the MPWME register.
12-Bit PWM generator OACSR Register OAON bit OAP VDD R1ext (I) (V) R 2ext OAN OAZ MCCFI MCCREF CEXT ADC VCREF + + Filter MREF Register CFAV bit
LEGEND: (I): Current mode (V): Voltage mode CLI: Current limitation interrupt MCFR register CFF[2:0] bits CLI
VCREF MAX = VDD Power down mode
Internal clock Sampling frequency
I
CFW[2:0] bits MCFR register
D
R
Q
To Phase State Control
CP S
Q
12-bit PWM generator/Compare U
V
MCRA Register V0C1 bit
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) This sets the minimum off time of the PWM signal generated by this internal clock. This off time can vary depending on the output of the current feedback comparator. In sensor mode (SR=1) and when the sampling for the Z event is done during the PWM ON time in sensorless mode (SPLG bit is set in MCRC register and /or DS[3:0] bits with a value other than 000 in MCONF register), there is no minimum OFF time required anymore, the minimum off time is set automatically to 0s and the OFF time of the PWM signal is controlled only by the current regulation loop. Table 47. Sampling Frequency Selection
SA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sampling Frequency 50.0 KHz 40.0 KHz 33.33 KHz 25.0 KHz 20.0 KHz 18.1 KHz 15.4 KHz 12.5 KHz 10 KHz 6.25 KHz 3.13 KHz 1.56 KHz 1.25 KHz 961 Hz 625 Hz 390 Hz
Warning: If the off time value set is superior than the period of the PWM signal (for example 40s off time for a 50KHz(25s period) PWM frequency), then the signal output on MCOx pins selected is a 100% duty cycle signal (always at 1). Table 48. Off time table
Sensor Mode Off Time sen- (SR=1) or samsorless mode pling during ON time in sensorOT3 OT2 OT1 OT0 (SR=0) less (SPLG =1 (DS[3:0]=0) and/or DS[3:0] bits) 0 0 0 0 2.5 s 0 0 0 1 5 s 0 0 1 0 7.5 s 0 0 1 1 10 s 0 1 0 0 12.5 s 0 1 0 1 15 s 0 1 1 0 17.5 s 0 1 1 1 20 s No minimum off time 1 0 0 0 22.5 s 1 0 0 1 25 s 1 0 1 0 27.5 s 1 0 1 1 30 s 1 1 0 0 32.5 s 1 1 0 1 35 s 1 1 1 0 37.5 s 1 1 1 1 40 s
Note: Times are indicated for 4 MHz fPERIPH Figure 105. Sampling clock generation block
MPRSR Register SA[3:0] bits 4
Note: Times are indicated for 4 MHz fPERIPH
fPERIPH
Frequency logic Off-Time logic 2 OT[3:0] bits MPWME Register
R S
Q
Tsampling
Toff (measurement window) Note: The MTC controller input frequency (fPERIPH) is 4 MHz in this example, It .can be configured to 8MHz with the XT16: XT8 bits in the MCONF register
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.9 Channel Manager The channel manager consists of: - A Phase State register with preload and polarity function Figure 106. Channel Manager Block Diagram
MCRA Register V0C1 bit PWM generator PWM Generator V Sampling frequency Current comparator output MCFR Register CFF[2:0] bits MCRA Register DAC bit C MPHST Register OO bits* MPAR Register OE[5:0] bits 6 6 Channel [5:0] Dead Time Dead Time Channel [5:0] MREF Register HFE[1:0] bits HFRQ[2:0] bits 6 High frequency chopper 5 Dead Time Phasen Register* SQ I I V
Notes:
Reg Regn I V Updated/Shifted on R Updated with Regn+1 on C
- A multiplexer to direct the PWM to the low and/ or high channel group - A tristate buffer asynchronously driven by an emergency input The block diagram is shown in Figure 106.
Current Mode Voltage Mode
Filter
R
events: C Commutation Z BEFM Zero-crossing DS,H End Of Demagnetization E Emergency Stop R+/- Ratio Updated (+1 or -1) O Multiplier Overflow
1
Branch taken after C event Branch taken after D event
2
MCRA Register SR bit
3
MCRB Register OS[2:0] bits*
8
MDTG Register
2
OCV bit
MPOL Register OP[5:0] bits MCRA Register MOE bit
x6 6 x6 1
1 CLIM bit 1 CLI bit 1
MCO2
NMCES
MCO5
MCO4
MCO3
* = Preload register, changes taken into account at next C event.
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MCO1
MCO0
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.9.1 MPHST Phase State Register A preload register enables software to asynchronously update the channel configuration for the next step (during the previous commutation interrupt routine for example): the OO[5:0] bits in the MPHST register are copied to the Phase register on a C event. Table 49. Output State
OP[5:0] bit 0 0 1 1 OO[5:0] bit 0 1 0 1 MCO[5:0] Pin 1 (OFF) 0-(PWM allowed) 0 (OFF) 1-(PWM allowed)
grammed using the OE[5:0] bits in the MPAR register. Table 51. Meaning of the OE[5:0] Bits
OE[5:0] 0 1 Channel group High channel Low channel
Direct access to the phase register is also possible when the DAC bit in the MCRA register is set. Note 1: In Direct Access Mode (DAC bit is set in MCRA register), a C event is generated as soon as there is a write access to OO[5:0] bits in MPHST register. Note 2: In Direct Access mode (DAC bit is set in MCRA register) the PWM application is selected by the OS0 bit in the MCRB register. Table 50. DAC and MOE Bit Meaning
MOE bit 0 1 DAC bit x 0 Effect on Output Reset state* Standard running mode MPHST register value (depending on MPOL, MPAR register values and PWM setting) see Table 75
1
1
*Note: The reset state of the outputs can be either high impedance, low or high state depending on the corresponding option bit. The polarity register is used to match the polarity of the power drivers keeping the same control logic and software. If one of the OPx bits in the MPOL register is set, this means the switch x is ON when MCOx is VDD. Each output status depends also on the momentary state of the PWM, its group (low or high), and the peripheral state. PWM Features The outputs can be split in two PWM groups in order to differentiate the high side and the low side switches. This output property can be pro-
The multiplexer directs the PWM to the upper channel, the lower channel or both of them alternatively or simultaneously according to the peripheral state. This means that the PWM can affect any of the upper or lower channels allowing the selection of the most appropriate reference potential when freewheeling the motor in order to: - Improve system efficiency - Speed up the demagnetization phase - Enable Back EMF zero crossing detection. The OS[2:0] bits in the MCRB register allow the PWM configuration to be configured for each case as shown in Figure 108 and Figure 107. During demagnetization, the OS2 bit is used to control PWM mode, and it is latched in a preload register so it can be modified when a commutation event occurs and the configuration is active immediately. The OS1 bit is used to control the PWM between the D and Z events to control back-emf detection. OS0 bit will allow to control the PWM signal between Z event and next C event. Note about demagnetization speed-up: during demagnetization the voltage on the winding has to be as high as possible in order to reduce the demagnetization time. Software can apply a different PWM configuration on the outputs between the C and D events, to force the free wheeling on the appropriate diodes to maximize the demagnetization voltage. 9.6.9.2 Emergency Feature When the NMCES pin goes low - The tristate output buffer is put in reset state asynchronously - The MOE bit in the MCRA register is reset - An interrupt request is sent to the CPU if the EIM bit in the MIMR register is set This bit can be connected to an alarm signal from the drivers, thermal sensor or any other security component. This feature functions even if the MCU oscillator is off.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 107. PWM application in Voltage or Current sensorless mode (see Table 62)
OS2 0 1 PWM behaviour after C and before D High Channels Low Channels OS1 0 1 PWM behaviour after D and before Z High Channels Low Channels Step Cn Demagnetization 1 0 D Demagnetization Wait Z event Z OS0 0 1 PWM behaviour after Z and before next C High Channels Low Channels
Off (0)
X
000 0 High 1 Low 001 0 High 1 Low 0 High 010 1 Low High 011 0 1 Low High 100 0 Low 1 High 101 0 1 Low High 110 0 1 Low 0 High 111 1 Low
Voltage (V0C1=x)
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On (1)
X
t] en Ev [5:0 OE 0] [2: OS :0] [5 OO de Mo
OS2
OS1
OS0
Delay
Cn+1
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 108. PWM application in Voltage or Current Sensor Mode (see Table 63)
OS2 0 1 PWM behaviour after C and before Z High Channels Low Channels Step Cn OS2 Wait Z event xx 1 0 Z OS0 Delay Delay OS1 (sensor mode: SR=1) Not Used OS0 0 1 PWM behaviour after Z and before next C High Channels Low Channels Cn+1 189/294
Off (0)
X 0x0 0x1 1x0 1x1
Voltage (V0C1=x)
On (1)
X
t en ] Ev [5:0 OE ] 0 [2: OS 0] [5: OO de Mo
0 High 1 Low 0 High 1 Low 0 High 1 Low 0 High 1 Low In sensor mode, there is no demagnetisation event and the PWM behaviour can be changed before and after Z event
1
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.9.3 Dead Time Generator When using typical triple half bridge topology for power converters, precautions must be taken to avoid short circuits in half bridges. This is ensured by driving high and low side switches with complementary signals and by managing the time between the switching-off and the switching-on instants of the adjacent switches. This time is usually known as deadtime and has to be adjusted depending on the devices connected to the PWM outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches,...). When driving motors in six-step mode, the deadtime generator function also allows synchronous rectification to be performed on the switch adjacent to the one where PWM is applied to reduce conduction losses. Figure 109. Dead Time waveforms
Reference Input signal 5V 0V Output A 5V Delay 0V 5V Output B Delay 0V
For each of the three PWM channels, there is one 6-bit Dead Time generator available. It generates two output signals: A and B. The A output signal is the same as the input phase signal except for the rising edge, which is delayed relative to the input signal rising edge. The B output signal is the opposite of the input phase signal except the rising edge which is delayed relative to the input signal falling edge. Figure 109 shows the relationship between the output signals of the deadtime register and its inputs. If the delay is greater than the width of the active phase (A or B) then the corresponding pulse is not generated (see Figure 110 and Figure 111).
Figure 110. Dead time waveform with delay greater than the negative PWM pulse
Input
5V 0V
Output A Delay
5V 0V 5V
Output B
0V
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 111. Dead Time waveform with delay greater than the positive PWM pulse
5V 0V 5V Output A 0V 5V Output B Delay 0V
Input
Table 52. Dead time programming and example
DTG5 DTG4
Tdtg 2xTmtc 4xTmtc 8xTmtc
Deadtime expression (DTG[4..0]+1) x Tdtg (DTG[3..0]+1) x Tdtg
Deadtime value From 1 to 32 Tdtg From 17 to 31 Tdtg
Tdtg @16MHz Fmtc 125ns 250ns 500ns
Dead time range @ 16MHz Fmtc 0.125s to 4s 4.25s to 8s 8.5s to 16s
0 1 1
X 0 1
The deadtime delay is the same for each of the channels and is programmable with the DTG[5..0] bits in the MDTG register. The resolution is variable and depends on the DTG5 and DTG4 bits. Table 52 summarizes the set-up of the deadtime generator. ITmtc is the period of the Dead Time Generator input clock (Fmtc = 16 MHz in most cases, not affected by the XT16:XT8 prescaler bits in the MCONF register). For safety reasons and since the deadtime depends only on external component characteristics (level-shifter delay, power components switching duration,...) the register used to set-up deadtime duration can be written only once after the MCU reset. This prevents a corrupted program counter modifying this system critical set-up, which may cause excessive power dissipation or destructive shoot-through in the power stage half bridges. When using the three independent U, V and W PWM signals (PCN bit set) (see Figure 112) to drive the MCOx outputs, deadtime is added as shown in Figure 109.
The dead time generator is enabled/disabled using the DTE bit. The effect of the DTE bit depends on the PCN bit value. If the PCN bit is set: s DTE is read only. To reset it, first reset the PCN bit, then reset DTE and set PCN to 1 again. s If DTE=0, the high and low side outputs are simply complemented (no deadtime insertion, DTG[5:0] bits are not significant); this is to allow the use of an external dead time generator. Note: The reset value of the MDTG register is FFh so when configuring the dead time, it is mandatory to follow one the two following sequences: s To use dead t imes while the PCN bit is set; from reset state write the MDTG value at once. The DTE bit will be read back as 1 whatever the programming value (read only if PCN=1) s To use dead times while the PCN bit is reset, write first the dead time value in DTG[5:0], then reset the PCN bit, or do both actions at the same time.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 112. Channel Manager Output Block Diagram with PWM generator delivering 3 PWM signals
PWM generator signals W Dead Time MREF Register HFE[1:0] bits HFRQ[2:0] bits 5 Channel [5:4] V Dead Time Channel [3:2] U Dead Time Channel [1:0]
8
MDTG Register PCN bit = 1
2
High frequency chopper
OCV bit
MPOL Register OP[5:0] bits MRCA Register MOE bit 6
x6
1 CLIM bit 1 CLI bit 1
x6 1
MCO2
NMCES
MCO5
MCO4
MCO3
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MCO1
MCO0
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) If the PCN bit is reset, one of the three PWM signals (the one set by the compare U register pair) or the output of the measurement window generator (depending on if the driving mode is voltage or current) is used to provide six-step signals through the PWM manager (to drive a PM BLDC motor for instance). In that case, DTE behaves like a standard bit (with multiple write capability). When the deadtime generator is enabled (bit DTE=1), some restrictions are applied, summarized in Table 53: s Channels are now grouped by pairs: Channel[0:1], Channel[2:3], Channel[4:5]; a deadtime generator is allocated to each of these pairs (see cautions below); s The input signal of the deadtime generator is the active output of the PWM manager for the corresponding channel. For instance, if we consider the Channel[0:1] pair, it may be either Channel0 or Channel1. s When both channels of a pair are inactive, the corresponding outputs will also stay inactive (this is mandatory to allow BEMF zero-crossing detection). Table 53 summarizes the functionality of the deadtime generator when the PCN bit is reset. 1(pwm*) means that the corresponding channel is active (1 in the corresponding bit in the MPHST register), and a PWM signal is applied on it (using the MPAR register and the OS[2:0] bits in MCRB register). PWM represents the complementary signals (although the duty cycle is slightly different due to deadtime insertion). 0 means that the channel is inactive and 1 means that the channel is active and a logic level 1 is applied on it (no PWM signal).
Table 53. Dead Time generator outputs
PCN = 0; DTE =1; x= 0, 2, 4 On/Off x (OOx bit) 0 1 (pwm*) 1 1 (pwm*) 1 0 0 On/Off x+1 (OOx+1 bit) 1 (pwm*) 0 1 (pwm*) 1 0 1 0 MCOx output PWM PWM 0 0 1 0 0 MCOx+1 output PWM PWM 0 0 0 1 0
* PWM generation enabled Warning: Grouping channels by pairs imposes the external connections between the MCO outputs and power devices; the user must therefore pay attention to respect the "recommended schematics" described in Figure 121. on page 224 and Figure 122 Note: As soon as the channels are grouped in pairs, special care has to be taken in configuring the MPAR register for a PM BLDC drive. If both channels of the same pair are both labelled "high" for example and if the PWM is applied on high channels, the active MCO output x (OOx=1 bit in the MPHST register) outputs PWM and the paired MCO output x+1 (OOx+1bit in the MPHST register) outputs PWM and vice versa. Caution: When PCN=0 and a complementary PWM is applied (DTE=1) on one channel of a pair, if both channels are active, this corresponds in output to both channels OFF. This is for security purpose to avoid cross-conduction. Caution: To clear the DTE bit from reset state of MDTG register (FFh), the PCN bit must be cleared before.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Figure 113. Channel Manager Output Block Diagram with PWM generator delivering 1 PWM signal
PWM generator U channel V S I Sampling frequency Current comparator output Phasen Register* 6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 R Q V I
MPAR Register OE[5:0] bits
Dead Time Channel [5:4] MREF Register HFE[1:0] bits HFRQ[2:0] bits 6
Dead Time Channel [3:2]
Dead Time Channel [1:0]
8
MDTG Register PCN bit = 0
2
High frequency chopper
5
OCV bit
MPOL Register OP[5:0] bits MCRA Register MOE bit
x6 6 x6 1
1 CLIM bit 1 CLI bit 1
MCO2
MCO5
MCO4
MCO3
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MCO1
MCO0
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.9.4 Programmable Chopper Depending on the application hardware, a chopper may be needed for the PWM signal. The MREF register allows the chopping frequency and mode to be programmed. The HFE[1:0] bits program the channels on which chopping is to be applied. The chopped PWM signal may be needed for high side switches only, low side switches or both of them in the same time (see Table 54). Table 54. Chopping mode
HFE[1:0] bits HFE1 HFE0 0 0 0 1 1 1 0 1 Chopping mode PCN bit =0 PCN bit =1 OFF OFF Low side switches Low channels only MCO1, 3, 5 High side switches High channels only MCO0, 2, 4 Both Low and High Both high and low channels sides
Table 55. Chopping frequency
Chopping frequency Chopping frequency
HFRQ2 HFRQ1 HFRQ0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Fmtc = 16MHz Fmtc = 4MHz Fmtc = 8MHz 100 KHz 50 KHz 200 KHz 100 KHz 400 KHz 200 KHz 500 KHz 250 KHz 800 KHz 400 KHz 1 MHz 500 KHz 1.33 MHz 666.66 MHz 2 MHz 1 MHz
The chopping frequency can any of the 8 values from 100KHz to 2MHz selected by the HFRQ[2:0] bits in the MREF register (see Table 55).
Note: When the PCN bit = 0: - If complementary PWM signals are not applied (DTE bit = 0), the high and low drivers are fixed by the MPAR register. Figure 106, Figure 112 and Figure 113 indicate where the HFE[1:0] bits are taken into account depending on the PWM application. - If complementary PWM signals are applied (DTE bit = 1), the channels are paired as explained in "Dead Time Generator" on page 190. This means that the high and low channels are fixed and the HFE[1:0] bits indicate where to apply the chopper. Figure 114 shows typical complementary PWM signals with high frequency chopping enabled on both high and low drivers.
Figure 114. Complementary PWM signals with chopping frequency on high and low side drivers.
Reference Input signal 5V 0V Output A 5V Delay 0V 5V Output B Delay 0V
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.10 PWM Generator Block The PWM generator block produces three independent PWM signals based on a single carrier frequency with individually adjustable duty cycles. Depending on the motor driving method, one or three of these signals may be redirected to the other functional blocks of the motor control peripheral, using the PCN bit in the MDTG register. When driving PM BLDC motors in six-step mode (voltage mode only, either sensored or sensorless) a single PWM signal (Phase U) is used to supply the Input Stage, PWM and Channel Manager blocks according to the selected modes. For other kind of motors requiring independent PWM control for each of the three phases, all PWM signals (Phases U, V and W) are directed to the channel manager, in which deadtime or a high Figure 115. PWM generator block diagram
U 12-bit Compare 0 Register MREP Register
frequency carrier may be added. This is the case of AC induction motors or PMAC motors for instance, supplied with 120 shifted sinewaves in voltage mode. 9.6.10.1 Main Features s 12-bit PWM free-running Up/Down Counter with up to 16MHz input clock (Fmtc). s Edge-aligned and center-aligned PWM operating modes s Possibility to re-load compare registers twice per PWM period in center-aligned mode s Full-scale PWM generation s PWM update interrupt generation s 8-bit repetition counter s 8-bit PWM mode s Timer re-synchronisation feature
Repetition counter Clear or Up/Down MPCR Register MPCR Register 12-bit PWM Counter CMS bit
U
Fmtc
Up to 16MHz
Prescaler PCP[2:0] bits
U
13-bit Compare U Register
U
13-bit Compare V Register
U
13-bit Compare W Register
Notes:
Reg Preload registers transferred to active registers on U event event: Update of compare registers PWM interrupt generation
U
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.10.2 Functional Description The 3 PWM signals are generated using a freerunning 12-bit PWM Counter and three 13-bit Compare registers for phase U, V and W: MCMPU, MCMPV and MCMPW registers. A fourth 12-bit register is needed to set-up the PWM carrier frequency: MCMP0 register. Each of these compare registers is buffered with a preload register. Transfer from preload to active registers is done synchronously with PWM counter underflow or overflow depending on configuration. This allows to write compare values without risks of spurious PWM transitions. The block diagram of the PWM generator is shown on Figure 115. 9.6.10.3 Prescaler The 12-bit PWM Counter clock is supplied through a 3-bit prescaler to allow the generation of lower PWM carrier frequencies. It divides Fmtc by 1, 2, 3, ..., 8 to get Fmtc-pwm. This prescaler is accessed through three bits PCP[2:0] in MPCR register; this register is buffered: the new value is taken into account after a PWM update event.
9.6.10.4 PWM Operating mode The PWM generator can work in center-aligned or edge-aligned mode depending on the CMS bit setting in the MPCR register. Figure 116 shows the corresponding counting sequence . It offers also an 8-bit mode to get a full 8-bit range with a single compare register write access by setting the PMS bit in MPCR register. The comparisons described here are performed between the PWM Counter value extended to 13 bits and the 13-bit Compare register. Having a compare range greater than the counter range is mandatory to get a full PWM range (i.e. up to 100% modulation). This principle is maintained for 8-bit PWM operations. s Center-aligned Mode (CMS bit = 1) In this operating mode, the PWM Counter counts up to the value loaded in the 12-bit Compare 0 register then counts down until it reaches zero and restarts counting up. The PWM signals are set to `0' when the PWM Counter reaches, in up-counting, the corresponding 13-bit Compare register value and they are set to `1' when the PWM Counter reaches the 13-bit Compare value again in down-counting.
Figure 116. Counting sequence in center-aligned and edge-aligned mode
center-aligned mode
0
1
2
....
15
16
15
....
2
1
0
1
T edge-aligned mode
0
1
2
.....
15
16
0
1
.....
16
0
1
T T = PWM period, Value of 12-bit Compare 0 Register= 16
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) If the 13-bit Compare register value is greater than the extended Compare 0 Register (the 13th bit is set to `0'), the corresponding PWM output signal is held at `1'.
If the 13-bit Compare register value is 0, the corresponding PWM output signal is held at `0'. Figure 117 shows some center-aligned PWM waveforms in an example where the Compare 0 register value = 8.
Figure 117. Center-aligned PWM Waveforms (Compare 0 Register = 8)
0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
1
1
2
3
`1'
4
`0' 1 Compare Register value = 4 2 Compare Register value = 7 3 Compare Register value > = 8 4 Compare Register value = 0
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) s Edge-aligned Mode (CMS bit = 0) In this operating mode, the PWM Counter counts up to the value loaded in the 12-bit Compare Register. Then the PWM Counter is cleared and it restarts counting up. The PWM signals are set to `0' when the PWM Counter reaches, in up-counting, the corresponding 13-bit Compare register value and they are set to `1' when the PWM Counter is cleared.
If the 13-bit Compare register value is greater than the extended Compare 0 register (the 13th bit is set to `0'), the corresponding PWM output signal is held at `1'. If the 13-bit Compare register value = 0, the corresponding PWM output signal is held at `0'. Figure 118 shows some edge-aligned PWM waveforms in an example where the Compare 0 register value = 8.
Figure 118. Edge-aligned PWM Waveforms (Compare 0 Register = 8)
0
1
2
3
4
5
6
7
8
0
1
1
2
3
`1'
4
`0' 1 Compare Register value = 4 2 Compare Register value = 8 3 Compare Register value > 8 4 Compare Register value = 0
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) s 12-bit Mode (PMS bit = 0 in the MPCR register) This mode is useful for MCMP0 values ranging from 9 bits to 12 bits. Figure 119 presents the way Compare 0 and Compare U, V, W should be loaded). It requires loading two bytes in the MCMPxH and MCMPxL registers (i.e. MCMP0, MCMPU, MCMPV and MCMPW 16-bit registers) following the sequence described below: - write to the MCMPxL register (LSB) first - then write to the MCMPxH register (MSB). The 16-bit value is then ready to be transferred in the active register as soon as an update event occurs. This sequence is necessary to avoid potential conflicts with update interrupts causing the hardware transfer from preload to active registers: if an update event occurs in the middle of the above sequence, the update is effective only when the MSB has been written. s 8-bit PWM mode (PMS bit = 1 in MPCR register) This mode is useful whenever the MCMP0 value is less or equal to 8-bits. It allows significant CPU re-
source savings when computing three-phase duty cycles during PWM interrupt routines. In this mode, the Compare 0 and Compare U, V, W registers have the same size (8 bits). The extension of the MCMPx registers is done in using the OVFx bits in the MPCR register (refer to Figure 119). These bits force the related duty-cycles to 100% and are reset by hardware on occurence of a PWM update event. Note about read access to registers with preload: during read accesses, values read are the content of the preload registers, not the active registers. Note about compare register active bit locations: the 13 active bits of the MCMPx registers are left-aligned. This allows temporary calculations to be done with 16-bit precision, round-up is done automatically to the 13-bit format when loading the values of the MCMPx registers. Note about MCMP0x registers: the configuration MCMP0H=MCMP0L=0 is not allowed
Figure 119. Comparison between 12-bit and 8-bit PWM mode b7 12-bit PWM mode (PMS bit = 0) MCMP0H b7
Ext
b0
b7 MCMP0L
b0
PWM frequency set-up Phase x duty cycle set-up
b0
b7 MCMPxL
b0
MCMPxH b7 8-bit PWM mode (PMS bit = 1)
OvfX
b0
b7 MCMP0L
b0
MCMP0H b7 MCMPxH b7
OvfU OvfV OvfW
PWM frequency set-up Phase x duty cycle set-up
b0
b7 MCMPxL
b0
b0 Equivalent bit location Ext Bit extending comparison range Bit not available
MPCR
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.10.5 Repetition Down-Counter Both in center-aligned and edge-aligned modes, the four Compare registers (one Compare 0 and three for the U, V and W phases) are updated when the PWM counter underflow or overflow and the 8-bit Repetition down-counter has reached zero. This means that data are transferred from the preload compare registers to the compare registers every N cycles of the PWM Counter, where N is the value of the 8-bit Repetition register in edge -aligned mode. When using center-aligned mode, the repetition down-counter is decremented every time the PWM counter overflows or underflows. Although this limits the maximum number of repetition to 128 PWM cycles, this makes it possible to update the duty cycle twice per PWM period. As a result, the effective PWM resolution in that case is equal to the resolution we can get using edge-
aligned mode, i.e. one Tmtc period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is 2xTmtc , due to the symmetry of the pattern. The repetition down counter is an auto-reload type; the repetition rate will be maintained as defined by the MREP register value (refer to Figure 120). 9.6.10.6 PWM interrupt generation A PWM interrupt is generated synchronously with the "U" update event, which allows to refresh compare values by software before the next update event. As a result, the refresh rate for phases duty cycles is directly linked to MREP register setting. A signal reflecting the update events may be output on a standard I/O port for debugging purposes. Refer to section9.6.7.3 on page 168 for more details.
Figure 120. Update rate examples depending on mode and MREP register settings Center-aligned mode
12-bit PWM Counter
Edge-aligned mode
MREP = 0
U
MREP = 1
U
MREP = 2
U
MREP = 3
MREP = 3 and re-synchronization
U
U (by SW) (by SW)
U
U Event: Preload registers transferred to active registers and PWM interrupt generated U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal to MCP0.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.10.7 Timer Re-synchronisation The 12-bit timer can be re-synchronized by a simple write access with FFh value in the MISR register. Re-synchronization means that the 12-bit counter is reset and all the compare preload registers MCP0, MCPU, MCPV, MCPW are transferred to the active registers. To re-synchronize the 12-bit timer properly , the following procedure must be applied: - 1. Load the new values in the preload compare registers - 2. Load FFh value in the MISR register (this will reset the counter and transfer the compare preload registers in the active registers: U event) - 3. Reset the PUI flag by loading 7Fh in the MISR register. Refer to Note 2 on page 205 Note: Loading FFh value in the MISR register will have no effect on any other flag than the PUI flag and will generate a PWM update interrupt if the PUM bit is set. Warning: In switched mode (SWA bit is reset), the procedure is the same and loading FFh in the MISR register will have no effect on flags except on the PUI flag. As a consequence, it is recommended to avoid setting RMI and RPI flags at the same time in switched mode because none of them will be taken into account. 9.6.10.8 PWM generator initialization and startup The three-phase generator counter stays in reset state (i.e. stopped and equal to 0), as long as MTC peripheral clock is disabled (CKE = 0). Setting the CKE bit has two actions on the PWM generator: s It starts the PWM counter s It forces the update of all registers with preload registers transferred on U update event, i.e. MREP, MPCR, MCMP0, MCMPU, MCMPV, MCMPW (in 12-bit mode, both MCMPxL and
MCMPxH must have been written, following the mandatory LSB/MSB sequence, before setting CKE bit). It consequently generates a U interrupt. 9.6.11 Low Power Modes Before executing a HALT or WFI instruction, software must stop the motor, and may choose to put the outputs in high impedance.
Mode WAIT Description
HALT
No effect on MTC interface. MTC interrupts exit from Wait mode. MTC registers are frozen. In Halt mode, the MTC interface is inactive. The MTC interface becomes operational again when the MCU is woken up by an interrupt with "exit from Halt mode" capability.
9.6.12 Interrupts
Interrupt Event Ratio increment Ratio decrement Speed Error Emergency Stop Current Limitation BEMF Zero-Crossing End of Demagnetization Commutation or Capture PWM Update Enable Event Control Flag Bit RPI RIM RMI SEI SEM EI EIM CLI CLIM ZI ZIM DI DIM CI PUI CIM PUM Exit from Wait Yes Yes Yes Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No No No No
The MTC interrupt events are connected to the three interrupt vectors (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) 9.6.13 Register Description TIMER COUNTER REGISTER (MTIM) Read /Write Reset Value: 0000 0000 (00h)
7 T7 6 T6 5 T5 4 T4 3 T3 2 T2 1 T1 0 T0
CAPTURE Zn REGISTER (MZREG) Read/Write Reset Value: 0000 0000 (00h)
7 ZC7 6 ZC6 5 ZC5 4 ZC4 3 ZC3 2 ZC2 1 ZC1 0 ZC0
Bits 7:0 = T[7:0]: MTIM Counter Value. These bits contain the current value of the 8-bit up counter. In Speed Measurement Mode, when using Encoder sensor and MTIM captures triggered by SW (refer to Figure 100) a read access to MTIM register causes a capture of the [MTIM:MTIML] register pair to the [MZREG: MZPRV] registers. TIMER COUNTER REGISTER LSB (MTIML) Read /Write Reset Value: 0000 0000 (00h)
7 TL7 6 TL6 5 TL5 4 TL4 3 TL3 2 TL2 1 TL1 0 TL0
Bits 7:0 = ZC[7:0]: Current Z Value or Speed capture MSB. These bits contain the current captured BEMF value (ZN) in Switched and Autoswitched mode or the MSB of the captured value of the [MTIM:MTIML] registers in Speed Sensor Mode. A read access to MZREG in this case disable the Speed captures up to MZPRV reading (refer to Section 9.6.7.5 Speed Measurement Mode on page 176). COMPARE C n+1 REGISTER (MCOMP) Read/Write Reset Value: 0000 0000 (00h)
7 DC7 6 DC6 5 DC5 4 DC4 3 DC3 2 DC2 1 DC1 0 DC0
Bits 7:0 = TL[7:0]: MTIM Counter Value LSB. These bits contain the current value of the least significant byte of the MTIM up counter, when used in Speed Measurement Mode (i.e. as a 16-bit timer) CAPTURE Zn-1 REGISTER (MZPRV) Read /Write Reset Value: 0000 0000 (00h)
7 ZP7 6 ZP6 5 ZP5 4 ZP4 3 ZP3 2 ZP2 1 ZP1 0
Bits 7:0 = DC[7:0]: Next Compare Value. These bits contain the compare value for the next commutation (CN+1). DEMAGNETIZATION REGISTER (MDREG) Read/Write Reset Value: 0000 0000 (00h)
7 DN7 6 DN6 5 DN5 4 DN4 3 DN3 2 DN2 1 DN1 0 DN0
ZP0
Bits 7:0 = ZP[7:0]: Previous Z Value or Speed capture LSB. These bits contain the previous captured BEMF value (ZN-1) in Switched and Autoswitched mode or the LSB of the captured value of the [MTIM:MTIML] registers in Speed Sensor Mode.
Bits 7:0 = DN[7:0]: D Value. These bits contain the compare value for simulated demagnetization (DN) and the captured value for hardware demagnetization (D H) in Switched and Autoswitched mode. In Speed Sensor Mode, the register contains the value used for comparison with MTIM registers to generate a Speed Error event.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) AN WEIGHT REGISTER (MWGHT) Read/Write Reset Value: 0000 0000 (00h)
7 AN7 6 AN6 5 AN5 4 AN4 3 AN3 2 AN2 1 AN1 0 AN0
INTERRUPT MASK REGISTER (MIMR) Read/Write Reset Value: 0000 0000 (00h)
7 PUM 6 SEM 5 RIM 4 CLIM 3 EIM 2 ZIM 1 DIM 0 CIM
Bits 7:0 = AN[7:0]: A Weight Value. These bits contain the AN weight value for the multiplier. In autoswitched mode the MCOMP register is automatically loaded with:
Zn x MWGHT 256(d) or ZN-1 x MWGHT 256(d) (*)
Bit 7 = PUM: PWM Update Mask bit. 0: PWM Update interrupt disabled 1: PWM Update interrupt enabled Bit 6 = SEM: Speed Error Mask bit. 0: Speed Error interrupt disabled 1: Speed Error interrupt enabled Bit 5 = RIM: Ratio update Interrupt Mask bit. 0: Ratio update interrupts (R+ and R-) disabled 1: Ratio update interrupts (R+ and R-) enabled Bit 4 = CLIM: Current Limitation Interrupt Mask bit. 0: Current Limitation interrupt disabled 1: Current Limitation interrupt enabled This interrupt is available only in Voltage Mode (VOC1 bit=0 in MCRA register) and occurs when the Motor current feedback reaches the external current limitation value. Bit 3 = EIM: Emergency stop Interrupt Mask bit. 0: Emergency stop interrupt disabled 1: Emergency stop interrupt enabled Bit 2 = ZIM: Back EMF Zero-crossing Interrupt Mask bit. 0: BEMF Zero-crossing Interrupt disabled 1: BEMF Zero-crossing Interrupt enabled Bit 1 = DIM: End of Demagnetization Interrupt Mask bit. 0: End of Demagnetization interrupt disabled 1: End of Demagnetization interrupt enabled if the HDM or SDM bit in the MCRB register is set Bit 0 = CIM: Commutation / Capture Interrupt Mask bit 0: Commutation / Capture Interrupt disabled 1: Commutation / Capture Interrupt enabled
when a Z event occurs. (*) depending on the DCB bit in the MCRA register. PRESCALER & SAMPLING REGISTER (MPRSR) Read/Write Reset Value: 0000 0000 (00h)
7 SA3 6 SA2 5 SA1 4 SA0 3 ST3 2 ST2 1 ST1 0 ST0
Bits 7:4 = SA[3:0]: Sampling Ratio. These bits contain the sampling ratio value for current mode. Refer to Table 47, "Sampling Frequency Selection," on page 185. Bits 3:0 = ST[3:0]: Step Ratio. These bits contain the step ratio value. It acts as a prescaler for the MTIM timer and is auto incremented/decremented with each R+ or R- event. Refer to Table 40, "Step Frequency/Period Range (4MHz)," on page 175 and Table 41, "Modes of Accessing MTIM Timer-Related Registers," on page 175.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) INTERRUPT STATUS REGISTER (MISR) Read/Write Reset Value: 0000 0000 (00h)
7 PUI 6 RPI 5 RMI 4 CLI 3 EI 2 ZI 1 DI 0 CI
1: Emergency stop interrupt pending Bit 2 = ZI: BEMF Zero-crossing interrupt flag. 0: No BEMF Zero-crossing Interrupt pending 1: BEMF Zero-crossing Interrupt pending Bit 1 = DI: End of Demagnetization interrupt flag. 0: No End of Demagnetization interrupt pending 1: End of Demagnetization interrupt pending Bit 0 = CI: Commutation / Capture interrupt flag 0: No Commutation / Capture Interrupt pending 1: Commutation / Capture Interrupt pending Note 1: Loading value FFh in the MISR register will reset the PWM generator counter and transfer the compare preload registers in the active registers by generating a U event (PUI bit set to 1). Refer to "Timer Re-synchronisation" on page 202. Note 2: In Autoswitched mode (SWA=1 in the MRCA register): As all bits in the MISR register are status flags, they are set by internal hardware signals and must be cleared by software. Any attempt to write them to 1 will have no effect (they will be read as 0) without interrupt generation. When several MTC interrupts are enabled at the same time the BRES instruction must not be used to avoid unwanted clearing of status flags: if a second interrupt occurs while BRES is executed (which performs a read-modify-write sequence) to clear the flag of a first interrupt, the flag of the second interrupt may also be cleared and the corresponding interrupt routine will not be serviced. It is thus recommended to use a load instruction to clear the flag, with a value equal to the logical complement of the bit. For instance, to clear the PUI flag: ld MISR, # 0x7F. In Switched mode (SWA=0 in the MRCA register): To avoid any losing any interrupts when modifying the RMI and RPI bits the following instruction sequence is recommended: ld MISR, # 0x9F ; reset both RMI & RPI bits ld MISR, # 0xBF ; set RMI bit ld MISR, # 0xDF ; set RPI bit
Bit 7 = PUI: PWM Update Interrupt flag. This bit is set by hardware when all the PWM Compare register are transferred from the preload to the active registers. The corresponding interrupt allows the user to refresh the preload registers before the next PWM update event defined with MREP register. 0: No PWM Update interrupt pending 1: PWM Update Interrupt pending Bit 6 = RPI: Ratio Increment interrupt flag. Autoswitched mode (SWA bit =1): 0: No R+ interrupt pending 1: R+ Interrupt pending Switched mode (SWA bit =0): 0: No R+ action 1: The hardware will increment the ST[3:0] bits when the next commutation occurs and shift all timer registers right. Speed Sensor mode (SWA bit =x, TES[1:0] bits =01, 10, 11): 0: No R+ interrupt pending 1: R+ Interrupt pending Bit 5 = RMI: Ratio Decrement interrupt flag. Autoswitched mode (SWA bit =1): 0: No R- interrupt pending 1: R- Interrupt pending Switched mode (SWA bit =0): 0: No R- action 1: The hardware will decrement the ST[3:0] bits when the next commutation occurs and shift all timer registers left. Speed Sensor mode (SWA bit =x, TES[1:0] bits =01, 10, 11): 0: No R- interrupt pending 1: R- Interrupt pending Bit 4 = CLI: Current Limitation interrupt flag. 0: No Current Limitation interrupt pending 1: Current Limitation interrupt pending Bit 3 = EI: Emergency stop Interrupt flag. 0: No Emergency stop interrupt pending
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) CONTROL REGISTER A (MCRA) Read/Write Reset Value: 0000 0000 (00h)
7 MOE 6 CKE 5 SR 4 DAC 3 V0C1 2 SWA 1 PZ 0 DCB
Table 56. Output configuration summary
CKE MOE DAC bit bit bit 0 0 x 0 1 0 Peripheral Clock Disabled Disabled Effect on MCOx Output Reset state Peripheral frozen (see note 1 below) Direct access via MPHST (only logical level) Reset state Standard running mode. Direct access via MPHST (PWM can be applied)
Bit 7 = MOE: Output Enable bit. 0: Outputs disabled 1: Outputs enabled
MOE bit 0 1 MCO[5:0] Output pin State Reset state Output enabled
0 1 1
1 0 1
1 x 0
Disabled Enabled Enabled
1
1
1
Enabled
Notes: - The reset state is either high impedance, high or low state depending on the corresponding option bit. - When the MOE bit in the MCRA register is reset (MCOx outputs in reset state), and the SR bit in the MCRA register is reset (sensorless mode) and the SPLG bit in the MCRC register is reset (sampling at PWM frequency) then, depending on the state of the ZSV bit in the MSCR register, Z event sampling can run or be stopped (and D event is sampled). Bit 6 = CKE: Clock Enable Bit. 0: Motor Control peripheral Clocks disabled 1: Motor Control peripheral Clocks enabled Note: Clocks disabled means that all peripheral internal clocks (Delay manager, internal sampling clock, PWM generator) are disabled. Therefore, the peripheral can no longer detect events and the preload registers do not operate. When Clocks are disabled, write accesses are allowed, so for example, MTIM counter register can be reset by software.
Note 1: "Peripheral frozen" configuration is not recommended, as the peripheral may be stopped in a unknown state (depending on PWM generator outputs,etc.). It is better practice to exit from run mode by first setting output state (by toggling either MOE or DAC bits) and then to disabling the clock if needed. Note 2: In Direct Access Mode (DAC=1), when CKE=0 (Peripheral Clock disabled) only logical level can be applied on the MCOx outputs when they are enabled whereas when CKE=1 (Peripheral Clock enabled), a PWM signal can be applied on them. Refer to Table 75, "DeadTime generator set-up," on page 217 Note 3: When clocks are disabled (CKE bit reset) while outputs are enabled (MOE bit set), the effects on the MCOx outputs where PWM signal is applied depend on the running mode selected: - in voltage mode (VOC1 bit=0), the MCOx outputs where PWM signal is applied stay at level 1. - in current mode (VOC1 bit=1), the MCOx outputs where PWM signal is applied are put to level 0. In all cases, MCOx outputs where a level 1 was applied before disabling the clocks stay at level 1. That is why it is recommended to disable the MCOx outputs (reset MOE bit) before disabling the clocks. This will put all the MCOx outputs under reset state defined by the corresponding option bit.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Effect on PWM generator: the PWM generator 12-bit counter is reset as soon as CKE = 0; this ensures that the PWM signals start properly in all cases. When these bits are set, all registers with preload on Update event are transferred to active registers. Bit 5 = SR: Sensor ON/OFF. 0: Sensorless mode 1: Position Sensor mode Table 57. Sensor Mode Selection
SR bit 0 Mode Sensors not used Sensors used OS[2:0] bits OS[2:0] bits enabled OS1 disabled Behaviour of the output PWM "Between Cn&D" behaviour, "between D&Z" behaviour and "between Z&Cn+1" behaviour "Between Cn&Z" behaviour and "between Z&Cn+1" behaviour
Table 58. DAC Bit Meaning
MOE bit 0 1 DAC bit x 0 Effect on Output Reset state depending on the option bit Standard running mode. MPHST register value (depending on MPOL, MPAR register values and PWM setting) see Table 75
1
1
Bit 3 = V0C1: Voltage/Current Mode 0: Voltage Mode 1: Current Mode Bit 2 = SWA: Switched/Autoswitched Mode 0: Switched Mode 1: Autoswitched Mode Table 59. Switched and Autoswitched Modes SWA
bit 0 1 Commutation Type Switched mode Autoswitched mode MCOMP Register access Read/Write Read/Write
1
See also Table 62 and Table 63 Bit 4 = DAC: Direct Access to phase state register. 0: No Direct Access (reset value). In this mode the preload value of the MPHST and MCRB registers is taken into account at the C event. 1: Direct Access enabled. In this mode, write a value in the MPHST register to access the outputs directly. Note: In Direct Access Mode (DAC bit is set in MCRA register), a C event is generated as soon as there is a write access to the OO[5:0] bits in MPHST register. In this case, the PWM low/high selection is done by the OS0 bit in the MCRB register.
Bit 1 = PZ: Protection from parasitic Zero-crossing event detection 0: Protection disabled 1: Protection enabled Note: If the PZ bit is set, the Z event filter (ZEF[3:0] in the MZFR register is ignored. Bit 0 = DCB: Data Capture bit 0: Use MZPRV (ZN-1) for multiplication 1: Use MZREG (ZN) for multiplication Table 60. Multiplier Result
DCB bit 0 1 Commutation Delay MCOMP = MWGHT x MZPRV / 256 MCOMP = MWGHT x MZREG / 256
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) CONTROL REGISTER B (MCRB) Read/Write Reset Value: 0000 0000 (00h)
7 0 6 CPB* 5 HDM* 4 SDM* 3 OCV 2 OS2* 1 OS1 0 OS0
Bit 7= Reserved, must be kept at reset value. Bit 6= CPB*: Compare Bit for Zero-crossing detection. 0: Zero crossing detection on falling edge 1: Zero crossing detection on rising edge Bit 5= HDM*: Hardware Demagnetization event Mask bit 0: Hardware Demagnetization disabled 1: Hardware Demagnetization enabled
Bits 2:0 = OS2*, OS[1:0]: Operating output mode Selection bits Refer to the Step behaviour diagrams (Figure 107, Figure 108) and Table 62, "Step Behaviour/ sensorless mode," on page 208. These bits are used to define the various PWM output configurations. Note: OS2 is the only preload bit. Table 62. Step Behaviour/ sensorless mode
OS2 bit PWM after PWM after PWM after OS1 Z and C and D and OS0 bit before next before D before Z C On high 0 channels On High 0 Channels On low 1 channels On High Channels On high 0 channels On Low 1 Channels On low 1 channels On high 0 channels On High 0 Channels On low 1 channels On Low Channels On high 0 channels On Low 1 Channels On low 1 channels
0
Bit 4= SDM*: Simulated Demagnetization event Mask bit 0: Simulated Demagnetization disabled 1: Simulated Demagnetization enabled Bit 3 = OCV: Over Current Handling in Voltage mode 0: Over Current protection is OFF 1:Over current protection is ON This bit acts as follows Table 61. Over current handling
CLIM bit CLI bit OCV bit 0 0 1 1 1 0 1 0 1 1 x x x 0 1 Output effect Interrupt Normal running No mode PWM is put off as No Current loop effect Normal running No mode PWM is put off as Yes Current loop effect All MCOx outputs are put in reset Yes state (MOE reset)
1
Note: For more details, see Step behaviour diagrams (Figure 107 and Figure 108). * Preload bits, new value taken into account at the next C event. A C event is generated at each write to MPHST in Direct Access mode.
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1
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Table 63. PWM mode when SR=1
OS2 bit PWM after PWM after Z OS1 C and Unused OS0 and before bit before Z next C On high 0 channels On High x x Channels On low 1 channels On high 0 channels On Low x x Channels On low 1 channels
SEI: Speed error interrupt flag 0: No Tacho Error interrupt pending 1: Tacho Error interrupt pending Bit 6= EDIR/HZ : Encoder Direction bit/ Hardware zero-crossing event bit Position Sensor or Sensorless mode (TES[1:0] bits =00): HZ: Hardware zero-crossing event bit This Read/Write bit selects if the Z event is hardware or not. 0: No hardware zero-crossing event 1: Hardware zero-crossing event Speed Sensor mode (TES[1:0] bits =01, 10, 11): EDIR:Encoder Direction bit This bit is Read only. As the rotation direction depends on encoder outputs and motor phase connections, this bit cannot indicate absolute direction. It therefore gives the relative phase-shift (i.e. advance/delay) between the two signals in quadrature output by the encoder (see Figure 88). 0: MCIA input delayed compared to MCIB input. 1: MCIA input in advance compared to MCIB input Bit 5 = SZ: Simulated zero-crossing event bit 0: No simulated zero-crossing event 1: Simulated zero-crossing event Bit 4 = SC: Simulated commutation event bit 0: Hardware commutation event in auto-switched mode (SWA = 1 in MCRA register) 1: Simulated commutation event in auto-switched mode (SWA = 1 in MCRA register).
0
1
Table 64. PWM mode when DAC=1
OS2 bit x Unused OS1 Unused OS0 bit 0 x x x 1 PWM on outputs On high channels On low channels
Warning: As the MCRB register contains preload bits with, it has to be written as a complete byte. A Bit Set or Bit Reset instruction on a non-preload bit will have the effect of resetting all the preload bits. CONTROL REGISTER C (MCRC) Read/Write (except EDIR bit) Reset Value: 0000 0000 (00h)
7 SEI / OI 6 EDIR/ HZ 5 4 3 2 1 0
SZ
SC
SPLG
VR2
VR1
VR0
Bit 7= SEI/OI: Speed Error interrupt flag / MTIM Overflow flag Position Sensor or Sensorless mode (TES[1:0] bits =00): OI: MTIM Overflow flag This flag signals an overflow of the MTIM timer. It has to be cleared by software. 0: No MTIM timer overflow 1: MTIM timer overflow Note: No interrupt is associated with this flag Speed Sensor mode (TES[1:0] bits =01, 10, 11):
Bit 3 = SPLG: Sampling Z event at high frequency in sensorless mode (SR=0) This bit enables sampling at high frequency in sensorless mode independently of the PWM signal or only during ON time if the DS[3:0] bits in the MCONF register contain a value. Refer to Table 78, "Sampling Delay," on page 220 0: Normal mode (Z sampling at PWM frequency at the end of the off time) 1: Z event sampled at fSCF (see Table 83) Note: When the SPLG bit is set, there is no minimum OFF time programmed by the OT [3:0] bits, the OFF time is forced to 0s. This means that in current mode, the OFF time of the PWM signal will come only from the current loop.
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1
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Bits 2:0 = VR[2:0]: BEMF/demagnetisation Reference threshold These bits select the Vref value as shown in the Table 65. The Vref value is used for BEMF and Demagnetisation detection. Table 65. Threshold voltage setting
VR2 1 1 1 1 0 0 0 0 VR1 1 1 0 0 1 1 0 0 VR0 1 0 1 0 1 0 1 0 Vref voltage threshold Threshold voltage set by external MCVREF pin 3.5V* 2.5V* 2V* 1.5V* 1V* 0.6V* 0.2V*
PHASE STATE REGISTER (MPHST) Read/Write Reset Value: 0000 0000 (00h)
7 IS1* 6 IS0* 5 OO5* 4 OO4* 3 OO3* 2 OO2* 1 OO1* 0 OO0*
Bit 7:6 = IS[1:0]*: Input Selection bits These bits mainly select the input to connect to comparator as shown in Table 66. The fourth configuration (IS[1:0] = 11) specifies that an incremental encoder is used (in that case MCIA and MCIB digital signals are directly connected to the incremental encoder interface and the analog multiplexer is bypassed. Table 66. Input Channel Selection
IS1 0 0 1 1 IS0 0 1 0 1 Channel selected MCIA MCIB MCIC Both MCIA and MCIB: Encoder Mode
*Typical values for VDD=5V
Bits 5:0 =OO[5:0]*: Channel On/Off bits These bits are used to switch channels on/off at the next C event if the DAC bit =0 or directly if DAC=1 0: Channel Off, the relevant switch is OFF, no PWM possible 1: Channel On the relevant switch is ON, PWM is possible (not signifiant when PCN bit is set). Table 67. OO[5:0] Bit Meaning
OO[5:0] 0 1 Output Channel State Inactive Active
* Preload bits, new value taken into account at next C event. Caution: As the MPHST register contains bits with preload, the whole register has to be written at once. This means that a Bit Set or Bit Reset instruction on only one bit without preload will have the effect of resetting all the bits with preload.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) MOTOR CURRENT FEEDBACK REGISTER (MCFR) Read/Write Reset Value: 0000 0000 (00h)
7 RPGS 6 RST 5 CFF2 4 CFF1 3 CFF1 2 1 0
Bits 2:0 = CFW[2:0]: Current Window Filter bits: These bits select the length of the blanking window activated each time PWM is turned ON. The filter blanks the output of the current comparator. Table 69. Current Feedback Window Setting
CFW2 CFW1 0 0 1 1 0 0 1 1 CFW0 0 1 0 1 0 1 0 1 Blanking Window Blanking window off 0.5s 1s 1.5s 2s 2.5s 3s 3.5s 0 0 0
CFW2 CFW1 CFW0
Bit 7= RPGS: Register Page Selection: 0: Access to registers mapped in page 0 1: Access to registers mapped in page 1 Bit 6= RST: Reset MTC registers. Software can set this bit to reset all MTC registers without resetting the ST7. 0: No MTC register reset 1: Reset all MTC registers Bits 5:3 = CFF[2:0]: Current Feedback Filter bits These bits select the number of consecutive valid samples (when the current is above the limit) needed to generate the active event. Sampling is done at fPERIPH/4. Table 68. Current Feedback Filter Setting
CFF2 0 0 0 0 1 1 1 1 CFF1 0 0 1 1 0 0 1 1 CFF0 0 1 0 1 0 1 0 1 Current Feedback Samples 1 2 3 4 5 6 7 8
0 1 1 1 1
Note: Times are indicated for 4 MHz fPERIPH
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1
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) MOTOR D EVENT FILTER REGISTER (MDFR) Read/Write Reset Value: 0000 1111 (0Fh)
7 DEF3 6 DEF2 5 DEF1 4 DEF0 3 2 1 0
Bit 3:0 = DWF[3:0]: D Window Filter bits These bits select the length of the blanking window activated at each C event. The filter blanks the D event detection. Table 71. D Window Filter setting
C to D Window Filter in SR=1 DWF3 DWF2 DWF1 DWF0 Sensorless mode (SR=0) 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5s 10s 15s 20s No window filter after C event 25s 30s 35s 40s 60s 80s 100s 120s 140s 160s 180s 200s
DWF3 DWF2 DWF1 DWF0
Bits 7:4 = DEF[3:0]: D Event Filter bits These bits select the number of valid consecutive D events (when the D event is detected) needed to generate the active event. Sampling is done at the selected fSCF frequency, see Table 83. Table 70. D Event filter Setting
DEF3 DEF2 DEF1 DEF0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D event Samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 No D Event Filter SR=1
0 0 0 0 0 0 1 1 1 1 1 1 1 1
Note: Times are indicated for 4 MHz fPERIPH
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) REFERENCE REGISTER (MREF) Read/Write Reset Value: 0000 0000 (00h)
7 HST 6 CL 5 4 3 2 1 0
Bits 4:3 = HFE[1:0]: Chopping mode selection These bits select the chopping mode as shown in the following table. Table 72. Chopping mode
HFE1 0 0 1 1 HFE0 0 1 0 1 Chopping mode OFF On Low channels only On High channels only Both High and Low channels
CFAV HFE1
HFE0 HFRQ2 HFRQ1 HFRQ0
Bit 7 = HST: Hysteresis Comparator Value. This read only bit contains the hysteresis comparator output. 0: Demagnetisation/BEMF comparator is under VREF 1: Demagnetisation/BEMF comparator is above VREF Bit 6 = CL: Current Loop Comparator Value. This read only bit contains the current loop comparator output value. 0: Current detect voltage is under VCREF 1: Current detect voltage is above VCREF Bit 5= CFAV: Current Feedback Amplifier entry Validation 0: OAZ is the current comparator entry 1: MCCFI is the current comparator entry
Bits 2:0 = HFRQ[2:0] : Chopper frequency selection These bits select the chopping frequency. Table 73. Chopping frequency selection
Chopping frequency Chopping frequency
HFRQ2 HFRQ1 HFRQ0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Fmtc = 16MHz Fmtc = 4MHz Fmtc = 8MHz 100 KHz 50 KHz 200 KHz 100 KHz 400 KHz 200 KHz 500 KHz 250 KHz 800 KHz 400 KHz 1 MHz 500 KHz 1.33 MHz 666.66 MHz 2 MHz 1 MHz
Note: The chopper signal has a 50% duty cycle.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) PWM CONTROL REGISTER (MPCR) Read/Write Reset Value: 0000 0000 (00h)
7 PMS OVFU OVFV OVFW CMS PCP2 PCP1 0 PCP0
Bit 4 = OVFW: Phase W 100% duty cycle Selection. 0: Duty cycle defined by MCPWH:MCPWL register. 1: Duty cycle set at 100% on phase W at next update event and maintained till the next one. This bit is reset once transferred to the active register on update event. Bit 3 = CMS: PWM Counter Mode Selection. 0: Edge-aligned mode 1: Center-aligned mode Bits 2:0 = PCP[2:0] PWM counter prescaler value. This value divides the Fmtc frequency by N, where N is PCP[2:0] value. Table 74 shows the resulting frequency of the PWM counter input clock. Table 74. PWM clock prescaler
PCP2 0 0 0 0 1 1 1 1 PCP1 0 0 1 1 0 0 1 1 PCP0 0 1 0 1 0 1 0 1 PWM counter input clock
Bit 7 = PMS: PWM Mode Selection. 0: Standard mode: bit b7 in the MCPxH register represents the extension bit. 1: "8-bit" mode: bit b7 (extension bit) in the MCPxH register is located in the MPCR register (OVFx bits); the number of active bits in MCPxH and MCPxL is decreased to b15:b8 instead of b15:b3. Bit 6 = OVFU: Phase U 100% duty cycle Selection. 0: Duty cycle defined by MCPUH:MCPUL register. 1: Duty cycle set at 100% on phase U at next update event and maintained till the next one. This bit is reset once transferred to the active register on update event. Bit 5 = OVFV: Phase V 100% duty cycle Selection. 0: Duty cycle defined by MCPVH:MCPVL register. 1: Duty cycle set at 100% on phase V at next update event and maintained till the next one. This bit is reset once transferred to the active register on update event.
Fmtc Fmtc/2 Fmtc/3 Fmtc/4 Fmtc/5 Fmtc/6 Fmtc/7 Fmtc/8
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) REPETITION COUNTER REGISTER (MREP) Read/Write Reset Value: 0000 0000 (00h)
7 REP7 REP6 REP5 REP4 REP3 REP2 REP1 0 REP0 CPWL CPWL CPWL CPWL CPWL 7 6 5 4 3 -
COMPARE PHASE W PRELOAD REGISTER LOW (MCPWL) Read/Write (except bits 2:0) Reset Value: 0000 0000 (00h)
7 0
Bits 7:0 = REP[7:0] Repetition counter value (N). This register allows the user to set-up the update rate of the PWM counter compare register (i.e. periodic transfers from preload to active registers), as well as the PWM Update interrupt generation rate, if these interrupts are enabled. Each time the MREP related Down-Counter reaches zero, the Compare registers are updated, a U interrupt is generated and it re-starts counting from the MREP value. After a microcontroller reset, setting the CKE bit in the MCRA register (i.e. enabling the clock for the MTC peripheral) forces the transfer from the MREP preload register to its active register and generates a U interrupt. During run-time (while CKE bit = 1) a new value entered in the MREP preload register is taken into account after a U event. As shown in Figure 120, (N+1) value corresponds to: - The number of PWM periods in edge-aligned mode - The number of half PWM periods in centeraligned mode. - COMPARE PHASE W PRELOAD REGISTER HIGH (MCPWH) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bits 7:5 = CPWL[7:3] Low bits of phase W preload value. Bits 2:0 = Reserved. COMPARE PHASE V PRELOAD REGISTER HIGH (MCPVH) Read/Write Reset Value: 0000 0000 (00h)
7 0
CPVH7 CPVH6 CPVH5 CPVH4 CPVH3 CPVH2 CPVH1 CPVH0
Bit 7:0 = CPVH[7:0] Most Significant Byte of phase V preload value COMPARE PHASE V PRELOAD REGISTER LOW (MCPVL) Read/Write (except bits 2:0) Reset Value: 0000 0000 (00h)
7 CPVL7 CPVL6 CPVL5 CPVL4 CPVL3 0 -
Bits 7:5 = CPVL[7:3] Low bits of phase V preload value. Bits 2:0 = Reserved.
CPWH CPWH CPWH CPWH CPWH CPWH CPWH CPWH 7 6 5 4 3 2 1 0
Bits 7:0 = CPWH[7:0] Most Significant Byte of phase W preload value
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) COMPARE PHASE U PRELOAD REGISTER HIGH (MCPUH) Read/Write Reset Value: 0000 0000 (00h)
7 0
COMPARE 0 PRELOAD REGISTER (MCP0L) Read/Write Reset Value: 1111 1111 (FFh)
7
LOW
0
CPUH CPUH CPUH CPUH CPUH CPUH CPUH CPUH 7 6 5 4 3 2 1 0
CP0L7 CP0L6 CP0L5 CP0L4 CP0L3 CP0L2 CP0L1 CP0L0
Bits 7:0 = CPUH[7:0] Most Significant Byte of phase U preload value COMPARE PHASE U PRELOAD REGISTER LOW (MCPUL) Read/Write Read/Write (except bits 2:0) Reset Value: 0000 0000 (00h)
7 CPUL7 CPUL6 CPUL5 CPUL4 CPUL3 0 -
Bits 7:0 = CP0L[7:0] Low byte of Compare 0 preload value. Note 1: The 16-bit Compare registers MCMPOx, MCMPUx, MCMPVx, MCMPWx MSB and LSB parts have to be written sequentially before being taken into account when an update event occurs; refer to section 9.6.10.4 on page 197 for details. Note 2: The CPB, HDM, SDM, OS2 bits in the MCRB and the bits OE[5:0] are marked with *. It means that these bits are taken into account at the following commutation event (in normal mode) or when a value is written in the MPHST register when in direct access mode. For more details, refer to the description of the DAC bit in the MCRA register. The use of a Preload register allows all the registers to be updated at the same time. Warning: Access to Preload registers Special care has to be taken with Preload registers, especially when using the ST7 BSET and BRES instructions on MTC registers. For instance, while writing to the MPHST register, you will write the value in the preload register. However, while reading at the same address, you will get the current value in the register and not the value of the preload register. Excepted for three-phase PWM generator's registers, all preload registers are loaded in the active registers at the same time. In normal mode this is done automatically when a C event occurs, however in direct access mode (DAC bit=1) the preload registers are loaded as soon as a value is written in the MPHST register. Caution: Access to write-once bits Special care has to be taken with write-once bits in MPOL and MDTG registers; these bits have to be accessed first during the set-up. Any access to the other bits (not write-once) through a BRES or a BSET instruction will lock the content of write-once bits (no possibility for the core do distinguish individual bit access: Read/write internal signal acts on a whole register only). This protection is then only unlocked after a processor hardware reset.
Bits 7:5 = CPUL[7:3] Low bits of phase U preload value. Bits 2:0 = Reserved. COMPARE 0 PRELOAD REGISTER (MCP0H) Read/Write (except bits 7:4) Reset Value: 0000 1111 (0Fh)
7 CP0H3 CP0H2 CP0H1
HIGH
0 CP0H0
Bits 7:4 = Reserved. Bits 3:0 = CP0H[3:0] Most Significant Bits of Compare 0 preload value.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) DEAD TIME GENERATOR REGISTER (MDTG) Read/Write (except bits 5:0 write once-only) Reset Value: 1111 1111 (FFh)
7 PCN DTE DTG5 DTG4 DTG3 DTG2 DTG1 0 DTG0
Bit 7 = PCN: Number of PWM Channels . 0: Only PWM U signal is output to the PWM manager for six-step mode motor control (e.g. PM BLDC motors) 1: The three PWM signals U, V and W are output to the channel manager (e.g. for three-phase sinewave generation) Bit 6 = DTE*: Dead Time Generator Enable 0: Disable the Dead Time generator 1: Enable the Dead Time generator and apply complementary PWM signal to the adjacent switch * write once-only bit if PCN bit is set, read/write if PCN bit is reset. To clear the DTE bit if PCN=1, it is mandatory to clear the PCN bit first. Table 75. DeadTime generator set-up
DAC 0 0 0 0 1 1 1 1 PCN bit DTE bit Complementary PWM in MDTG in MDTG applied to adjacent register register switch 0 0 NO 0 1 YES 1 1 YES YES, but 1 0 WITHOUT deadtime NO Complementary 0 0 PWM 0 1 YES 1 1 YES YES, but 1 0 WITHOUT deadtime
When the PCN bit is reset (e.g. for PM BLDC motors), in Direct Access mode (DAC=1), if the DTE bit is reset, PWM signals can be applied on the MCOx outputs but not complementary PWM. Of course, logical levels can be also applied on the outputs. If the DTE bit is set (PCN=0 and DAC=1), channels are paired and complementary PWM signals can be output on the MCOx pins. This will follow the rules detailed in Table 53, "Dead Time generator outputs," on page 193 as the channels are grouped in pairs. In this case, the PWM application is selected by the OS0 bit in the MCRB register. It is also possible to add a chopper on the PWM signal output using bits HFE[1:0] and HFRQ[2:0] in the MREF register. Caution 1: The PWM mode will be selected via the 00[5:0] bits in the MPHST register, the OE[5:0] bits in the MPAR register and the OS2 and OS0 bits in the MCRB register as shown in Table 63, "PWM mode when SR=1," on page 209. Caution 2: When driving motors with three independent pairs of complementary PWM signals (PCN=1), disabling the deadtime generator (DTE=0) causes the deadtime to be null: high and low side signals are exactly complemented. It is therefore recommended not to disable the deadtime generator (it may damage the power stage), unless deadtimes are inserted externally. Bits 5:0 = DTG[5:0]* Dead time generator set-up. These bits set-up the deadtime duration and resolution. Refer to Table 52, "Dead time programming and example," on page 191 for details. With Fmtc = 16MHz dead time values range from 125ns to 16s with steps of 125ns, 250ns and 500ns. * Write-once bits; once write-accessed these bits cannot be re-written unless the processor is reset (See "Caution: Access to write-once bits" on page 216.).
Note 1: This table is true on condition that the CKE bit is set (Peripheral clock enabled) and the MOE bit is set (MCOx outputs enabled). See Table 56, "Output configuration summary," on page 206
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) POLARITY REGISTER (MPOL) Read/Write (some bits write-once) Reset Value: 0011 1111 (3Fh)
7 ZVD 6 REO 5 OP5 4 OP4 3 OP3 2 OP2 1 OP1 0 OP0
Bit 7 = ZVD: Z vs D edge polarity. 0: Zero-crossing and End of Demagnetisation have opposite edges 1: Zero-crossing and End of Demagnetisation have same edge Bit 6 = REO: Read on High or Low channel bit 0: Read the BEMF signal on High channels 1: Read on Low channels Note: This bit always has to be configured whatever the sampling method. Bits 5:0 = OP[5:0]*: Output channel polarity. These bits are used together with the OO[5:0] bits in the MPHST register to control the output channels. 0: Output channel is Active Low 1: Output channel is Active High. * Write-once bits; once write-accessed these bits cannot be re-written unless the processor is reset (See "Caution: Access to write-once bits" on page 216.). Table 76. Output Channel State Control
OP[5:0] bit 0 0 1 1 OO[5:0] bit 0 1 0 1 MCO[5:0] pin 1 (Off) 0 (PWM possible) 0 (Off) 1 (PWM possible)
Warning: OP[5:0] bits in the MPOL register must be configured as required by the application before enabling the MCO[5:0] outputs with the MOE bit in the MCRA register.
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) PWM REGISTER (MPWME) Read/Write Reset Value: 0000 0000 (00h)
7 DG 6 5 4 3 OT3 2 OT2 1 OT1 0 OT0
Bits 3:0 = OT[3:0]: Off Time selection These bits are used to select the OFF time in sensorless current mode as shown in the following table. Table 77. OFF time bits
Off Time sensorless mode OT3 OT2 OT1 OT0 (SR=0) (DS[3:0]=0) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2.5 s 5 s 7.5 s 10 s 12.5 s 15 s 17.5 s 20 s 22.5 s 25 s 27.5 s 30 s 32.5 s 35 s 37.5 s 40 s Sensor Mode (SR=1) or sampling during ON ime in sensorless (SPLG =1 and/or DS [3:0] bits)
PWMW PWMV PWMU
Bit 7 = DG:Debug Option. This bit is used to enter debug mode. As a result, C, D and Z events are output on 2 pins MCDEM and MCZEM in Switched and Autoswitched mode, C and U events are output in Speed Measurement mode. Refer to section9.6.7.3 on page 168 for more details 0: Normal mode 1: Debug mode Bit 6 = PWMW: PWM W output control 0: PWM on Compare Register W is not output on MCPWMW pin 1: PWM on Compare Register W is output on MCPWMW pin Bit 5 = PWMV: PWM V output control 0: PWM on Compare Register V is not output on MCPWMV pin 1: PWM on Compare Register V is output on MCPWMV pin Bit 4 = PWMU: PWM U output control 0: PWM on Compare Register U is not output on MCPWMU pin 1: PWM on Compare Register U is output on MCPWMU pin
No minimum off time
Note: Times are indicated for 4 MHz fPERIPH
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) CONFIGURATION REGISTER (MCONF) Read/Write Reset Value: 0000 0010 (02h)
7 DS3 6 DS2 5 DS1 4 DS0 3 SOI 2 SOM 1 XT16 0 XT8
during the next Toff. In this case, the sample is discarded. 0: No Sampling Out Interrupt Pending 1: Sampling Out Interrupt Pending Bit 2 = SOM: Sampling Out Mask bit. This interrupt is available only for Z event sampling as D event sampling is always done at fSCF high frequency. 0: Sampling Out interrupt disabled 1: Sampling Out interrupt enabled This interrupt is available only when a delay has been set in the DS[3:0] bits in the MCONF register. Note: It is recommended to disable the sampling out interrupt when software Z event is enabled (SZ bit in MCRC register is set) and if the value in the DS[3:0] bits is modified to change the sampling method during the application. Bits [1:0] = XT16:XT8 BLDC drive Motor Control Peripheral input frequency selection: Table 79. Peripheral frequency XT16
0 0 1 1
Bits 7:4 = DS[3:0]: Delay for sampling at Ton These bits are used to define the delay inserted before sampling in order to sample during PWM ON time. Table 78. Sampling Delay
DS3 DS2 DS1 DS0 Delay added to sample at Ton 0 0 0 0 No delay added. Sample during Toff 0 0 0 1 2.5 s 0 0 1 0 5 s 0 0 1 1 7.5 s 0 1 0 0 10 s 0 1 0 1 12.5 s 0 1 1 0 15 s 0 1 1 1 17.5 s 1 0 0 0 20 s 1 0 0 1 22.5 s 1 0 1 0 25 s 1 0 1 1 27.5 s 1 1 0 0 30 s 1 1 0 1 32.5 s 1 1 1 0 35 s 1 1 1 1 37.5 s
XT8
0 1 0 1
Peripheral frequency fPERIPH=fMTC fPERIPH=fMTC/2 fPERIPH=fMTC/4 fPERIPH=fMTC/4
(same as XT16=1,XT8=0)
Note: Times are indicated for 4 MHz fPERIPH Bit 3 = SOI Sampling Out Interrupt flag. This interrupt indicates that the sampling that should have been done during Ton has occured
Caution: It is recommended to set the peripheral frequency to 4MHz. Setting fPERIPH=fMTC is used mainly when fOSC2 = 4MHz (for low power consumption).
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) PARITY REGISTER (MPAR) Read/Write Reset Value: 0000 0000 (00h)
7 TES1 6 TES0 5 OE5 4 OE4 3 OE3 2 OE2 1 OE1 0 OE0
TES 1 0 0 1 1
TES 0 0 1 0 1
Edge sensitivity Not applicable Rising edge Falling edge Rising and falling edges
Operating Mode Position Sensor or Sensorless Speed Sensor Speed Sensor Speed Sensor
Bits 7:6 = TES[1:0] : Tacho Edge Selection bits The primary function of these bits is to select the edge sensitivity of the tachogenerator capture logic; clearing both TES[1:0] bits specifies that the Input Detection block does not operate in Speed Sensor Mode but either in Position Sensor or Sensorless Mode for a six-step motor drive).
Bits 5:0 = OE[5:0]: Output Parity Mode. 0: Output channel is High 1: Output channel Low Note: These bits are not significant when PCN=1 (configuration with three independent phases).
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) MOTOR Z EVENT FILTER REGISTER (MZFR) Read/Write Reset Value: 0000 1111 (0Fh)
7 ZEF3 6 ZEF2 5 ZEF1 4 ZEF0 3 2 1 0
Bits 3:0 = ZWF[3:0]: Z Window Filter bits These bits select the length of the blanking window activated at each D event. The filter blanks the Z event detection until the end of the time window. Table 82. Z Window filter Setting
D to Z window filZWF3 ZWF2 ZWF1 ZWF0 ter in Sensorless Mode (SR=0) 0 0 0 0 5 s 0 0 0 1 10 s 0 0 1 0 15 s 0 0 1 1 20 s 0 1 0 0 25 s 0 1 0 1 30 s 0 1 1 0 35 s 0 1 1 1 40 s 1 0 0 0 60 s 1 0 0 1 80 s 1 0 1 0 100 s 1 0 1 1 120 s 1 1 0 0 140 s 1 1 0 1 160 s 1 1 1 0 180 s 1 1 1 1 200 s SR=1
ZWF3 ZWF2 ZWF1 ZWF0
Bits 7:4 = ZEF[3:0]: Z Event Filter bits These bits select the number of valid consecutive Z events (when the Z event is detected) needed to generate the active event. Sampling is done at the selected fSCF frequency (see Table 83.) or at PWM frequency. Table 81. Z Event filter Setting
ZEF3 ZEF2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ZEF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ZEF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z event Samples 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
No Window Filter after D event
Note: Times are indicated for 4 MHz fPERIPH
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) MOTOR SAMPLING CLOCK (MSCR) Read/Write Reset Value: 0000 0000 (00h)
7 ZSV 6 0 5 0 4 0 3 SCF1 2 SCF0
REGISTER
1 ECM
0 DISS
Bit 7 = ZSV Z Event Sampling Validation when MOE bit is reset This bit enables/disables Z event sampling in either mode (sampling at PWM frequency or at fSCF frequency selected by SCF[1:0] bits) 0: Z event sampling disabled 1: Z event sampling enabled Bits 6:4 = Reserved, must be kept cleared. Bits 3:2 = SCF[1:0] Sampling Clock Frequency These bits select the sampling clock frequency (fSCF) used to count D & Z events. Table 83. Sampling Clock Frequency
SCF1 0 0 1 1 SCF0 0 1 0 1
Bit 1 = ECM: Encoder Capture Mode This bit is used to select the source of events which trigger the capture of the [MTIM:MTIML] counter when using Encoder speed sensor (see Figure 88). 0: Real Time Clock interrupts 1: Read access on MTIM register Bit 0 = DISS Data Input Selection This setting is effective only if PCN=0, TES=00 and SR=0. 0: Unused MCIx inputs are grounded 1: Unused MCIx inputs are put in HiZ
fSCF
1 MHz (every 1s) 500 kHz (every 2s) 250 kHz (every 4s) 125 kHz (every 8s)
Note: Times are indicated for 4 MHz fPERIPH
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Microcontroller DS,H CS,H D/Z Window filter
2
Board + Motor ISn bit MCIA MCIB
1
2
R MCPWMU 1 /20 MCPWMV MCPWMW SR bit OSn bits
12-bit PWM generator
+
+1
1 1/128 3 MREF Reg
MTIM = FFh?
1/2
ST3-0 bits
4
1 / 2Ratio
MPWME Reg
MTIM [8-bit Up Counter] Dead Time
0
clr
1
CH
Ch0
ZH Ch2 DH Ch3 SQ R Ch4 Dead Time MDREG Reg [Dn]
Ch1
MPHSTn Reg
ZS,H Compare SDMn bit Ch5
drivers
High Frequency Chopper
Dead Time
ZWF[3:0] Filter / D
ZS
DWF[3:0] Filter / C
MOE bit
MCOMP Reg [Cn+1] CL R-/+ E ZS,H DS,H CS,H
MPAR Reg
MDTG register PCN bit =0
OAON
MPOL Reg
CLI bit
+ CLI
CLIM bit
Compare
OCV bit
CFF[2:0] bit
MISR Reg
MIMR Reg
CFW[2:0] bit
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MCIC Q
1
ZH D
Z event generation
MCVREF CS,H VREF DS,H VR2-0
DH CP SPLG
D event generation
ST7MC1/ST7MC2
XT16:XT8 bit
Fmtc
V I
Fperiph
PRESCALER
1/4
Compare U
HV
-1
SWA bit Z V I
MZREG < 55h? MCO0 MCO2
R-
ck
SA3-0 & OT1-0 bits
8
x6
x6
MCO4 B
MZREG Reg [Zn]
A MCO1 MCO3 MCO5 C
MZPRV Reg [Zn-1]
Compare
Figure 121. Detailed view of the MTC for PM BLDC motor control
DCB bit DS,H DS 6
n-1 n
SZn bit
MWGHT Reg [an+1]
8
8
8 2 6
6
1
NMCES MCPWMU/V/W
A x B / 256
SWA bit
8
OAP OAN OAZ
CS,H
A
+ CFAV bit MCCFI MCCREF
VDD (I) (V)
Cext
R1ext
R2ext
Microcontroller
Board + Motor
Fmtc
Direction EDIR bit TES bits
MCIB MCIA MCIA MCIB ISn bit
up to 16MHz Encoder interface Incremental Encoder
Encoder Clock
IS[1:0] bits TES[1:0] bits
R+
E
Tachogenerator
+1 C 1 / 2Ratio MTIM Read RTC interrupt ECM bit IS[1:0] bits TES[1:0] bits
MCIC MCIA or MCIB or MCIC
MTIM = FFh?
ST[3:0] Bits
Clock Ratio
Capture Tacho
or
or
4
T
-1
MZREG < 55h?
R-
Clock clr C
MTIM
16-bit Up Counter
MTIML
MSbits
MREF Reg
LSbits
C
C
HV
MZREG 16-bit Capture register FFh (Fixed) U 13-bit Compare U Register
Dead Time
MZPRV
MCO0
MDREG
Phase U
MCO2
x6
x6
MCO4 B
Compare Phase V
Dead Time
Compare
drivers
U 13-bit Compare V Register
Three-phase Induction motor
A MCO1 MCO3 C
Phase W U 13-bit Compare W Register
Dead Time
High Frequency Chopper
S
MCO5 8 2
6 6
1 MOE bit
E NMCES OAON
Fmtc
12-bit PWM Counter Clear or Up/Down
Up to 16MHz PWM Clock
PCP[2:0] bits
MPCR Register
MDTG register PCN bit =1
MPAR Reg
MPOL Reg
U
CL MREP Reg
U
Repetition Counter
+ -
OAP OAN OAZ
R-/+
Figure 122. Detailed view of the MTC configured for Induction motor control (proposal)
E
U
12-bit Compare 0 Register
MISR Reg
MIMR Reg
S
+
CL
MCCFI
U
-
CFAV bit MCCREF
ST7MC1/ST7MC2
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C
ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont'd) Table 84. MTC Page 0 Register Map and Reset Values
Register Name MTIM Reset Value MTIML Reset Value MZPRV Reset Value MZREG Reset Value MCOMP Reset Value MDREG Reset Value MWGHT Reset Value MPRSR Reset Value MIMR Reset Value MISR Reset Value MCRA Reset Value MCRB Reset Value MCRC Reset Value MPHST Reset Value MDFR Reset Value MCFR Reset Value MREF Reset Value MPCR Reset Value MREP Reset Value MCPWH Reset Value 7 T7 0 TL7 0 ZP7 0 ZC7 0 DC7 0 DN7 0 AN7 0 SA3 0 PUM 0 PUI 0 MOE 0 0 SEI / OI 0 IS1 0 DEF3 0 RPGS 0 HST 0 PMS 0 REP7 0 CPWH7 0 6 T6 0 TL6 0 ZP6 0 ZC6 0 DC6 0 DN6 0 AN6 0 SA2 0 SEM 0 RPI 0 CKE 0 CPB 0 EDIR / HZ 0 IS0 0 DEF2 0 RST 0 CL 0 OVFU 0 REP6 0 CPWH6 0 5 T5 0 TL5 0 ZP5 0 ZC5 0 DC5 0 DN5 0 AN5 0 SA1 0 RIM 0 RMI 0 SR 0 HDM 0 SZ 0 OO5 0 DEF1 0 CFF2 0 CFAV 0 OVFV 0 REP5 0 CPWH5 0 4 T4 0 TL4 0 ZP4 0 ZC4 0 DC4 0 DN4 0 AN4 0 SA0 0 CLIM 0 CLI 0 DAC 0 SDM 0 SC 0 OO4 0 DEF0 0 CFF1 0 HFE1 0 OVFW 0 REP4 0 CPWH4 0 3 T3 0 TL3 0 ZP3 0 ZC3 0 DC3 0 DN3 0 AN3 0 ST3 0 EIM 0 EI 0 V0C1 0 OCV 0 SPLG 0 OO3 0 DWF3 1 CFF0 0 HFE0 0 CMS 0 REP3 0 CPWH3 0 2 T2 0 TL2 0 ZP2 0 ZC2 0 DC2 0 DN2 0 AN2 0 ST2 0 ZIM 0 ZI 0 SWA 0 OS2 0 VR2 0 OO2 0 DWF2 1 CFW2 0 HFRQ2 0 PCP2 0 REP2 0 CPWH2 0 1 T1 0 TL1 0 ZP1 0 ZC1 0 DC1 0 DN1 0 AN1 0 ST1 0 DIM 0 DI 0 PZ 0 OS1 0 VR1 0 OO1 0 DWF1 1 CFW1 0 HFRQ1 0 PCP1 0 REP1 0 CPWH1 0 0 T0 0 TL0 0 ZP0 0 ZC0 0 DC0 0 DN0 0 AN0 0 ST0 0 CIM 0 CI 0 DCB 0 OS0 0 VR0 0 OO0 0 DWF0 1 CFW0 0 HFRQ0 0 PCP0 0 REP0 0 CPWH0 0
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ST7MC1/ST7MC2
Register Name MCPWL Reset Value MCPVH Reset Value MCPVL Reset Value MCPUH Reset Value MCPUL Reset Value MCP0H Reset Value MCP0L Reset Value 7 CPWL7 0 CPVH7 0 CPVL7 0 CPUH7 0 CPUL7 0 0 CP0L7 1 6 CPWL6 0 CPVH6 0 CPVL6 0 CPUH6 0 CPUL6 0 0 CP0L6 1 5 CPWL5 0 CPVH5 0 CPVL5 0 CPUH5 0 CPUL5 0 0 CP0L5 1 4 CPWL4 0 CPVH4 0 CPVL4 0 CPUH4 0 CPUL4 0 0 CP0L4 1 3 CPWL3 0 CPVH3 0 CPVL3 0 CPUH3 0 CPUL3 0 CP0H3 1 CP0L3 1 2 0 CPVH2 0 0 CPUH2 0 0 CP0H2 1 CP0L2 1 1 0 CPVH1 0 0 CPUH1 0 0 CP0H1 1 CP0L1 1 0 0 CPVH0 0 0 CPUH0 0 0 CP0H0 1 CP0L0 1
Table 85. MTC Page 1 Register Map and Reset Values
Register Name MDTG Reset Value MPOL Reset Value MPWME Reset Value MCONF Reset Value MPAR Reset Value MZFR Reset Value MSCR Reset Value 7 PCN 1 ZVD 0 DG 0 DS3 0 TES1 0 ZEF3 0 ZSV 0 6 DTE 1 REO 0 PWMW 0 DS2 0 TES0 0 ZEF2 0 0 5 DTG5 1 OP5 1 PWMV 0 DS1 0 OE5 0 ZEF1 0 0 4 DTG4 1 OP4 1 PWMU 0 DS0 0 OE4 0 ZEF0 0 0 3 DTG3 1 OP3 1 OT3 0 SOI 0 OE3 0 ZWF3 1 SCF1 0 2 DTG2 1 OP2 1 OT2 0 SOM 0 OE2 0 ZWF2 1 SCF0 0 1 DTG1 1 OP1 1 OT1 0 XT16 1 OE1 0 ZWF1 1 ECM 0 0 DTG0 1 OP0 1 OT0 0 XT8 0 OE0 0 ZWF0 1 DISS 0
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Figure 123. Page Mapping for Motor Control
PAGE 0 MTIM MTIML MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MCRC MPHST MDFR MCFR MREF MPCR MREP MCPWH MCPWL MCPVH MCPVL MCPUH MCPUL MCPOH MCPOL PAGE 1 RPGS bit =1 in MCFR register 50 51 52 53 54 55 56 MDTG MPOL MPWME MCONF MPAR MZFR MSCR
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9.7 OPERATIONAL AMPLIFIER (OA) 9.7.1 Introduction The ST7 Op-Amp module is designed to cover various types of microcontroller applications where analog signals amplifiers are used. It may be used to perform a variety of functions such as: differential voltage amplifier, comparator/ threshold detector, ADC zooming, impedance adaptor, general purpose operational amplifier. 9.7.2 Main Features This module includes: s 1 stand alone Op-Amp that may be externally connected using I/O pins s Op-Amp output can be internally connected to the ADC inputs as well as to the motor control current feedback comparator input s Input offset compensation with optional average s On/Off bit to reduce power consumption and to enable the input/output connections with external pins 9.7.3 General Description This Op-Amp can be used with 3 external pins (see device pinout description) and can be internally connected to the ADC and the Motor Control cells. The gain must be fixed with external components. The input/output pins are connected to the OpAmp as soon as it is switched ON (through the OACSR register). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the "I/O ports" chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. The output is not connected (HiZ) when the OpAmp is OFF. However the pin can still be used as an ADC or MTC input in this case. When the Op-Amp is ON the output is connected to a dedicated pin which is not a standard I/O port. The output can be also be connected to the ADC or the MTC. The switches are controlled software (refer to the MTC and ADC chapters). 9.7.4 Input Offset Compensation The Op-Amp incorporates a method to minimize the input offset which is dependant on process lot. It is useable by setting the OFFCMP bit of the control register, which launch the compensation cycle. The CMPVR bit is set by hardware as soon as this cycle is completed. The compensation is valid as long as the OFFCMP bit is high. It can be re-performed by cycling OFFCMP `0' then `1'. The compensation can be improved by averaging the calculation (over 16 times) setting the AVGCMP bit.
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ST7MC1/ST7MC2
OP-AMP MODULE (Cont'd) 9.7.5 Op-Amp Programming The flowchart for Op-Amp operation is shown in Figure 124 Figure 124. Normal Op-Amp Operation. Power On Reset OACSR = 0000 0000
External components always connected
(1)
Write OACSR = x0010xx0 Wait for Amplifier to wake up (Twakeup)
Compensation Offset ? (4) Write OACSR = x0p1 pxx0 p : same as before Yes Yes
No
Average Compensation ? (2b)
No
(2a) Write OACSR = x111 0xx0 Wait for 24576*TCPU cycles Read CMPOVR = 1
Write OACSR = x101 0xx0 Wait for 1536*TCPU cycles Read CMPOVR = 1
#OFFCMP & AVGCMP should be set simultenaously
Need closed loop gain > 20dB @ 100kHz ?
Yes
No Yes Re-compensate Offset ? No Op-Amp useable
(3) # Write OACSR = x1p1 1xx0 p : same as before
#The HIGHGAIN bit can also be written in step (1) or (2)
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ST7MC1/ST7MC2
OP-AMP MODULE (Cont'd) 9.7.6 Low power modes Note: The Op-Amp can be disabled by resetting the OAON bit. This feature allows reduced power consumption when the amplifier is not used. Mode WAIT HALT Description
No effect on Op-Amp Op-Amp disabled After wake-up from Halt mode, the OpAmp requires a stabilization time (see Electrical characteristics) (to be defined)
9.7.8 Register Description CONTROL/STATUS REGISTER (OACSR) Read /Write (except bit 7 read only) Reset Value: 0000 0000(00h)
7
CMP OVR
6
OFF CMP
5
AVG CMP
4
OAO N
3
HIGH GAIN
2
0
1
0
0
0
9.7.7 Interrupts None.
Bit 7 = CMPOVR Compensation Completed This read-only bit contains the offset compensation status. 0: No offset compensation if OFFCMP = 0, or Offset compensation cycle not completed if OFFCMP = 1 1: Offset compensation completed if OFFCMP = 1 Bit 6 = OFFCMP Offset Compensation 0: Reset offset compensation values 1: Request to start offset compensation Bit 5 = AVGCMP Average Compensation 0: One-shot offset compensation 1: Average offset compensation over 16 times Bit 4 = OAON Amplifier On 0: Op-Amp powered off 1: Op-Amp on Bit 3 = HIGHGAIN Gain range selection This bit must be programmed depending on the application. It can be used to ensure 35dB open loop gain when high, it must be low when the closed loop gain is below 20dB for stability reasons. 0: Closed loop gain up to 20dB 1: Closed loop gain more than 20dB Bits 2:0 = Reserved, must be kept cleared.
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ST7MC1/ST7MC2
9.8 10-BIT A/D CONVERTER (ADC) 9.8.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. 4 of the channels have dedicated circuitry and pins to reduce noise and leakage so as to improve the accuracy and reduce the sensitivity to analog source impedance. The result of the conversion is stored in 2 8-bit Data Registers. The A/D converter is controlled through a Control/Status Register. 9.8.2 Main Features s 10-bit conversion s Up to 16 channels with multiplexed input s 2 software-selectable sample times s External positive reference voltage VREF+ can be independent from supply Figure 125. ADC Block Diagram fADC Linear successive approximation Data registers (DR) which contain the results s Conversion complete status flag s Maskable interrupt s On/off bit (to reduce consumption) The block diagram is shown in Figure 125.
s s
9.8.3 Functional Description 9.8.3.1 Analog References VREF+ and VREF- are the high and low level reference voltage pins. Conversion accuracy may therefore be impacted by voltage drops and noise on these lines. VREF+ can be supplied by an intermediate supply between VDDA and VSSA to change the conversion voltage range. VREF- must be tied to VSSA. An internal resistor bridge is implemented between VREF+ and VREF- pins, with a typical value of 15k 9.8.3.2 Analog Power Supply VDDA and VSSA are the supply and ground pins providing power to the converter part. They must
PRESCALER
EOC PRSC1PRSC0 ADON CS3
CS2
CS1
CS0
ADCCSR
4
IT request
AIN0
ADSTS ADCIE
AIN1
MCCBCR
ANALOG MUX
ANALOG TO DIGITAL CONVERTER
AINx
ADCDRMSB
D9
D8
D7
D6
D5
D4
D3
D2
ADCDRLSB
0
0
0
0
0
0
D1
D0
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ST7MC1/ST7MC2
10-BIT A/D CONVERTER (ADC) (Cont'd) 9.8.3.3 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VREF+ (high-level voltage reference) then the conversion result is FFh in the ADCDRMSB register and 03h in the ADCDRLSB register (without overflow indication). If the input voltage (VAIN) is lower than VREF- (lowlevel voltage reference) then the conversion result in the ADCDRMSB and ADCDRLSB registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRMSB and ADCDRLSB registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. RREF is the value of the resistive bridge implemented in the device between VREF+ and VREF-. 9.8.3.4 A/D Conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. If the application used the high-impedance analog inputs, then the sample time should be stretched by setting the ADSTS bit in the MCCBCR register. In the ADCCSR register: - Select the CS[3:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: - Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. - The EOC bit is kept low by hardware during the conversion. Note: Changing the A/D channel during conversion will stop the current conversion and start conversion of the newly selected channel.
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ST7MC1/ST7MC2
10-BIT A/D CONVERTER (ADC) (Cont'd) When a conversion is complete: - The EOC bit is set by hardware - An interrupt request is generated if the ADCIE bit in the MCCBCR register is set (see section 5.4.7 on page 33). - The result is in the ADCDR registers and remains valid until the next conversion has ended. To read the 10 bits, perform the following steps: 1. Poll the EOC bit or wait for EOC interrupt 2. Read ADCDRLSB 3. Read ADCDRMSB The EOC bit is reset by hardware once the ADCDRMSB is read. To read only 8 bits, perform the following steps: 1. Poll the EOC bit or wait for EOC interrupt 2. Read ADCDRMSB The EOC bit is reset by hardware once the ADCDRMSB is read. Changing the conversion channel The application can change channels during conversion. In this case the current conversion is stopped and the A/D converter starts converting the newly selected channel. ADCCR consistency If an End Of Conversion event occurs after software has read the ADCDRLSB but before it has read the ADCDRMSB, there would be a risk that the two values read would belong to different samples. To guarantee consistency: - The ADCDRMSB and the ADCDRLSB are locked when the ADCCRLSB is read - The ADCDRMSB and the ADCDRLSB are unlocked when the MSB is read or when ADON is reset. Thus, it is mandatory to read the ADCDRMSB just after reading the ADCDRLSB. Otherwise the ADCDR register will not be updated until the ADCDRMSB is read. 9.8.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wake up from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed.
HALT
9.8.5 Interrupts
Interrupt Event End of Conversion
1)The
Event Flag EOC
Enable Control Bit ADCIE1)
Exit from Wait Yes
Exit from Halt No
ADCIE bit is in the MCCBCR register (see section 5.4.7 on page 33)
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ST7MC1/ST7MC2
10-BIT A/D CONVERTER (ADC) (Cont'd) 9.8.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read /Write (Except bit 7 read only) Reset Value: 0000 0000 (00h)
7
EOC PRSC1 PRSC0 ADON CS3 CS2 CS1
0
CS0
DATA REGISTER (ADCDRMSB) Read Only Reset Value: 0000 0000 (00h)
7
D9 D8 D7 D6 D5 D4 D3
0
D2
Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRMSB register. 0: Conversion is not complete 1: Conversion complete Bit 6:5 = PRSC[1:0] ADC clock prescaler selection These bits are set and cleared by software.
fADC 4MHz 2MHz 1MHz PRSC1 0 0 1 PRSC0 0 1 0
Bit 7:0 = D[9:2] MSB of Analog Converted Value This register contains the MSB of the converted analog value. DATA REGISTER (ADCDRLSB) Read Only Reset Value: 0000 0000 (00h)
7 0
0 0 0 0 0 D1 D0
Bit 4 = ADON A/D Converter on This bit is set and cleared by software. 0: Disable ADC and stop conversion 1: Enable ADC and start conversion Bit 3:0 = CS[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
Bit 7:2 = Reserved. Forced by hardware to 0. Bit 1:0 = D[1:0] LSB of Analog Converted Value This register contains the LSB of the converted analog value.
*The number of channels is device dependent. Refer to the device pinout description.
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ST7MC1/ST7MC2
10-BIT A/D CONVERTER (ADC) (Cont'd) Table 86. ADC Register Map and Reset Values
Address (Hex.) 2E 2F 30 Register Label ADCCSR Reset Value ADCDRMSB Reset Value ADCDRLSB Reset Value 7 EOC 0 D9 0 0 0 6 PRSC1 0 D8 0 0 0 5 PRSC0 0 D7 0 0 0 4 ADON 0 D6 0 0 0 3 CS3 0 D5 0 0 0 2 CS2 0 D4 0 0 0 1 CS1 0 D3 0 D1 0 0 CS0 0 D2 0 D0 0
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ST7MC1/ST7MC2
10 INSTRUCTION SET
10.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do Table 87. CPU Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination
Pointer Address (Hex.)
Pointer Size (Hex.)
Length (Bytes) +0 +1
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
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INSTRUCTION SET OVERVIEW (Cont'd) 10.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
10.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 10.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 10.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
10.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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INSTRUCTION SET OVERVIEW (Cont'd) 10.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 88. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function
10.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Available Relative Direct/Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Function
Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont'd) 10.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. INT pin = 1 Jump if ext. INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) jrf * (ext. INT pin high) (ext. INT pin low) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst Src M M M M I1 H H H I0 N N N N N Z Z Z Z Z C C C
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt 1 1 1 0 N Z reg, M reg, M reg, M reg, M A reg, M M 1 1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 1 0 N N Z Z C C A=A+M pop reg pop CC push Y C=0 A reg CC M M M M reg, CC 0 I1 H I0 N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src I1 H I0 N Z C
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11 ELECTRICAL CHARACTERISTICS
11.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 11.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 11.1.2 Typical values Unless otherwise specified, typical data are based on TA=25C, VDD=5V. They are given only as design guidelines and are not tested. 11.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 11.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 126. Figure 126. Pin loading conditions Figure 127. Pin input voltage
ST7 PIN
VIN
ST7 PIN
CL
11.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 127.
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11.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi11.2.1 Voltage Characteristics
Symbol VDD - VSS VPP - VSS VIN |VDDx| and |VSSx| |VSSA - VSSx| VESD(HBM) VESD(MM) Supply voltage Programming Voltage Input voltage on any pin 1) & 2) Variations between different digital power pins Variations between digital and analog ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Ratings
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Maximum value 6.5 13 VSS-0.3 to VDD+0.3 50 50
Unit V
mV
see section 11.7.3 on page 259
11.2.2 Current Characteristics
Symbol Ratings 32-pins devices IVDD Total current into VDD power lines (source) 3) 44-pins devices 56, 64, 80-pins devices 32-pins devices IVSS Total current out of VSS ground lines (sink) 3) 44-pins devices 56, 64, 80-pins devices Maximum value 75 125 175 75 125 175 25 50 - 25 5 5 5 5 20 mA Unit
Output current sunk by any standard I/O and control pin IIO Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on VPP pin IINJ(PIN) 2) & 4) Injected current on RESET pin Injected current on OSC1 and OSC2 pins Injected current on any other pin 5) IINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5)
Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN244/294
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11.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C
Maximum junction temperature (see Section 12.2 THERMAL CHARACTERISTICS)
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11.3 6OPERATING CONDITIONS 11.3.1 General Operating Conditions
Symbol fCPU Parameter Internal clock frequency versus VDD Extended operating voltage VDD Standard operating voltage Operating voltage for flash Write/Erase TA Ambient temperature range VPP = 11.4 to 12.6V 6 Suffix Version C Suffix Version No Flash Write/Erase. Analog parameters not guaranteed Conditions Min 0 3.8 4.5 4.5 -40 -40 Max 8 5.5 5.5 5.5 85 125 C V Unit MHz
Figure 128. fCPU Max Versus VDD
fCPU [MHz]
8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA
6
4 2 1 0 3.5 3.8 4.0 4.5 5.5 SUPPLY VOLTAGE [V]
FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE SPECIFIED IN THE TABLES OF PARAMETRIC DATA)
Note: Some temperature ranges are only available with a specific package and memory size. Refer to Ordering Information. Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.
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OPERATING CONDITIONS (Cont'd) 11.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fOSC, and TA.
Symbol VIT+(LVD) VIT-(LVD) Vhys(LVD) VtPOR tg(VDD) Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time rate 1) Width of filtered glitches on VDD 1) (which are not detected by the LVD) VIT+(LVD)-VIT-(LVD) 20 100 40 Conditions Min 4.0 1) 3.8 Typ 4.2 4.0 200 Max 4.5 V 4.25 mV s/V ms/V ns Unit
Notes: 1. Data based on characterization results, not tested in production.
11.3.3 Auxiliary Voltage Detector (AVD) Thresholds Subject to general operating condition for VDD, fOSC, and TA.
Symbol VIT+(AVD) VIT-(AVD) Vhyst(AVD) VITParameter 10 AVDF flag toggle threshold (VDD rise) 01 AVDF flag toggle threshold (VDD fall) AVD voltage threshold hysteresis) Voltage drop between AVD flag set and LVD reset activated) VIT+(AVD)-VIT-(AVD) VIT-(AVD)-VIT-(LVD) Conditions Min 4.4 1) 4.2 1) Typ 4.7 4.5 200 450 Max 4.9 1) V 4.7 1) mV mV Unit
Notes: 1. Data based on characterization results, not tested in production.
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11.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped). 11.4.1 RUN and SLOW Modes (Flash devices)
Symbol Parameter Supply current in RUN mode (see Figure 129) IDD 4.5VVDD5.5V
2)
Conditions fOSC=16MHz, fCPU=8MHz
Typ 12
Max 1) 18
Unit mA
Supply current in SLOW mode 2) (see Figure 130)
fOSC=16MHz, fCPU=500kHz
5
8
mA
Figure 129. Typical IDD in RUN vs. fCPU
16.0 14.0 12.0
Idd (mA)
Figure 130. Typical IDD in SLOW vs. fCPU
3.0 2.5 2.0 Idd (mA) 1.5 1.0
10.0 8.0 6.0 4.0 2.0 0.0 0 1 2 3 4
Fcpu Mhz
0.5 0.0
5
6
7
8
0
1
2
3
4 Fcpu Mhz
5
6
7
8
Notes: 1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Measurements are done in the following conditions: - Progam executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%. - All I/O pins in input mode with a static value at VDD or VSS (no load) - All peripherals in reset state. - LVD disabled. - Clock input (OSC1) driven by external square wave. - In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32. To obtain the total current consumption of the device, add the clock source (Section 11.5.3) and the peripheral power consumption.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 11.4.2 WAIT and SLOW WAIT Modes
Symbol Parameter Supply current in WAIT mode (see Figure 131) IDD 4.5VVDD5.5V
2)
Conditions fOSC=16MHz, fCPU=8MHz
Typ 8
Max 1) 12
Unit
Supply current in SLOW WAIT mode 2) (see Figure 132)
mA fOSC=16MHz, fCPU=500kHz 3.5 5
Figure 131. Typical IDD in WAIT vs. f CPU
8.0 7.0 6.0 Idd (mA)
Figure 132. Typical IDD in SLOW-WAIT vs. fCPU
2.5
2.0
4.0 3.0 2.0
Idd (mA) 0 1 2 3 4 Fcpu Mhz 5 6 7 8
5.0
1.5
1.0
0.5 1.0 0.0 0.0 0 1 2 3 4 Fcpu Mhz 5 6 7 8
Notes: 1. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. Measurements are done in the following conditions: - Progam executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%. - All I/O pins in input mode with a static value at VDD or VSS (no load) - All peripherals in reset state. - LVD disabled. - Clock input (OSC1) driven by external square wave. - In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32. To obtain the total current consumption of the device, add the clock source (Section 11.5.3) and the peripheral power consumption.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 11.4.3 HALT and ACTIVE-HALT Modes
Symbol IDD Parameter Supply current in HALT mode 1) Supply current in ACTIVE-HALT mode 2) VDD=5.5V Conditions -40CTA+85C -40CTA+125C 16Mhz external clock Typ 0 1 Max 10 50 1.5 Unit A mA
1. All I/O pins in push-pull output mode (when applicable) with a static value at VDD or VSS (no load), PLL and LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 2. All I/O pins in input mode with a static value at VDD or VSS. Tested in production at VDD max and fcpu max with clock input OSC1 driven by an external square wave; VDD apllied on OSC2 to reduce oscillator consumption. Consumption may be slightly different with a quartz or resonator.
11.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Symbol IDD(LVD) IDD(PLL) Parameter LVD supply current PLL supply current VDD = 5V Conditions HALT mode Typ 150 700 Max 1) 300 Unit A
Notes: 1. Data based on characterization results, not tested in production.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 11.4.5 On-Chip Peripherals
Symbol IDD(TIM) IDD(ART) IDD(SPI) IDD(SCI) IDD(MTC) IDD(ADC) Parameter 16-bit Timer supply current 1) ART PWM supply current 2) SPI supply current
3)
Conditions fCPU=8MHz fCPU=8MHz fCPU=8MHz fCPU=8MHz fCPU=8MHz fADC=4MHz fCPU=8MHz VDD=5.0V VDD=5.0V VDD=5.0V VDD=5.0V VDD=5.0V VDD=5.0V VDD=5.0V
Typ 50 75 400 400 500 400 1500
Unit
SCI supply current 4) MTC supply current 5) ADC supply current when converting 6)
A
IDD(OPAMP) OPAMP supply current 7)
Notes: 1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer. 2. Data based on a differential IDD measurement betwwen reset configuration (timer stopped ) and timer counter enable (only TCE bit set ) 3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption. 4. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data transmit sequence. 5. Data based on a differnetial IDD measurement between reset configuration (motor control disabled) and the whole motor control cell enable in speed measurement mode. MCO outputs are not validated. 6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. 7. Data based on a differential measurement between reset configuration (OPAMP disabled) and amplification of a sinewave (no load, AVCL=1, VDD=5V).
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11.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 11.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 1) 3 375
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution.
11.5.2 External Clock Source
Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) IL Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 1) OSC1 rise or fall time 1) OSCx Input leakage current VSSVINVDD see Figure 133 Conditions Min 0.7xVDD VSS 25 ns 5 1 A Typ Max VDD 0.3xVDD Unit V
Figure 133. Typical Application with an External Clock Source
90% VOSC1H 10% VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
VDD OSC2
fOSC EXTERNAL CLOCK SOURCE OSC1 IL ST7FMC
Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) 11.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as
Symbol fOSC RF CL1 CL2 i2 Parameter Oscillator Frequency 1) Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS) OSC2 driving current VDD=5V VIN=VSS
close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Conditions Min 4 TBD Max 16 TBD Unit MHz k pF A
See table below TBD TBD
Oscil. Ceramic MP MS HS MURATA
Typical Crystal or Ceramic Resonators Reference CSTCR4M00G53 CSTCE8M00G53 CSTCE16M0V53 Freq. 4MHz 8MHz 16MHz Characteristic 2)
CL1 [pF] 22 33 33
CL2 [pF] 22 33 33
Figure 134. Typical Application with a Crystal or Ceramic Resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS
i2
fOSC OSC1
CL1
RESONATOR CL2 OSC2
RF ST7FMC
Notes: 1. When PLL is used, please refer to the PLL characteristics chapter and to the "supply, reset and clock management" description chapter (fOSC min is 8 Mhz with PLL). 2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) 11.5.4 Clock Security System with PLL Table 89. PLL Characteristics
Symbol Fosc Output Frequency tLock Jitter fcpu Parameter PLL input frequency range Output frequency when the PLL attain lock. PLL Lock Time (LOCKED = 1) Jitter in the output clock CPU clock frequency when VCO is connected to ground (ICD internal clock or back up oscillator ) Min 7 16 50 2 3 100 Typ Max 8 Unit MHz MHz s % MHz
Table 90. Clock Detector Characteristics
Symbol fDetect tsetup thold Notes: 1. Data based on characterization results, not tested in production. Parameter Detected Minimum Input Frequency Time needed to detect OSCIN once CKD is enabled Time needed to detect that OSCIN stops 3 3 Min Typ Max 500 1) Unit KHz s s
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) Table 91. PLL And Clock Detector Signal Start Up Sequence
OSCIN PLLEN (PLL and CKD) PLL CLOCK t lock LOCK PLL clock CKSEL fCLK
2) 1)
16Mhz
fVCO= 6 Mhz
OSCIN Clock
3)
CSSD
t setup
4)
t hold
CSSIE
INTERRUPT
Notes: 1. Lock does not go low without resetting the PLLEN bit. 2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of tlock must have elapsed. 3. 2 clock cycles are missing after CKSEL = 1 4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1 ).
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11.6 MEMORY CHARACTERISTICS 11.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 1.6
Typ
Max
Unit V
11.6.2 FLASH Memory
DUAL VOLTAGE HDFLASH MEMORY Symbol Parameter fCPU VPP IPP tVPP tRET NRW TPROG TERASE Operating frequency Programming voltage 3) VPP current4) 5) Internal VPP stabilization time Data retention Write erase cycles Programming or erasing temperature range Conditions Read mode Write / Erase mode 4.5V VDD 5.5V Read (VPP=12V) Write / Erase TA=55C TA=25C Min 2) 0 1 11.4 Typ Max 2) 8 8 12.6 200 30 Unit MHz V A mA s years cycles C
10 20 100 -40 25 85
Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Not tested in production. 2. Data based on characterization results, not tested in production. 3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons. 4. Data based on simulation results, not tested in production 5. In Write/Erase mode the IDD supply current consumption is the same as in Run mode (section 11.4.1 on page 248 )
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11.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 11.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). s ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. s FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 11.7.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It
Symbol Parameter
SC=8MHz,
should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015) .
Level/ Class 4A
Conditions
VFESD
Flash device, VDD=5V, TA=+25C, fOLVD OFF Voltage limits to be applied on any I/O pin to induce a conforms to IEC 1000-4-2 functional disturbance Flash device, VDD=5V, TA=+25C, fOSC=8MHz, LVD ON conforms to IEC 1000-4-2 VDD=5V, TA=+25C, fOSC=8MHz, PLL OFF Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a func- conforms to IEC 1000-4-4 tional disturbance VDD=5V, TA=+25C, fOSC=8MHz, PLL ON conforms to IEC 1000-4-4
2B
3B 4A
VFFTB
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EMC CHARACTERISTICS (Cont'd) 11.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin.
Symbol Parameter Conditions VDD=5V, TA=+25C conforming to SAE J 1752/3 Device/ Package Monitored Frequency Band 0.1MHz to 30MHz Flash/TQFP64 30MHz to 130MHz 130MHz to 1GHz SAE EMI Level Max vs. [fOSC/fCPU] 8/4MHz 8 8 1 1.5 16/8MHz 6 12 9 2.5 dBV Unit
SEMI
Peak level
Notes: 1. Data based on characterization results, not tested in production. 2. Refer to Application Note AN1709 for data on other package types
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EMC CHARACTERISTICS (Cont'd) 11.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
11.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.
Absolute Maximum Ratings
Symbol VESD(HBM) VESD(MM) Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) TA=+25C TA=+25C Conditions Maximum value 1) Unit 2500 V 250
Notes: 1. Data based on characterization results, not tested in production.
11.7.3.2 Static and Dynamic Latch-Up s LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class
s
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
Conditions TA=+25C TA=+125C VDD=5.5V, fOSC=4MHz, TA=+25C
Class 1) A A A
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
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11.8 I/O PORT PIN CHARACTERISTICS 11.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys VIL VIH Vhys IINJ(PIN)3) Parameter Input low level voltage
1)
Conditions CMOS ports
Min 0.7xVDD
Typ
Max 0.3xVDD
Unit V V
Input high level voltage 1) Schmitt trigger voltage hysteresis 2) Input low level voltage
1)
1
0.8
Input high level voltage 1) Schmitt trigger voltage hysteresis 2) Injected Current on an I/Os exept PD7
G & H ports
2.8
V mV
400 +5/-2 VDD=5V +5/-0 25 VSSVINVDD 11 200 80 120 5 25 25 1 250
IINJ(PIN)3) Injected Current on PD7 Total injected current (sum of all I/O IINJ(PIN)3) and control pins) IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Input leakage current Static current consumption I/O pin capacitance Output high to low level fall time 1) External interrupt pulse time 6)
4)
mA
Floating input mode VIN=VSS VDD=5V
A k pF ns tCPU
Weak pull-up equivalent resistor 5)
CL=50pF Output low to high level rise time 1) Between 10% and 90%
Notes: 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN260/294
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 135. Two typical Applications with unused I/O Pin
VDD 10k
Figure 136. Typical Rpu vs. VDD with VIN=VSS
ST7FMC
UNUSED I/O PORT
10k
UNUSED I/O PORT
ST7FMC
TBD
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I/O PORT PIN CHARACTERISTICS (Cont'd) 11.8.2 Output Driving Current Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 137) VDD=5V Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 138) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 139) Conditions IIO=+5mA IIO=+2mA IIO=+20mA, TA85C TA85C IIO=+8mA IIO=-5mA, TA85C VDD-1.4 TA85C VDD-1.6 VDD-0.7 IIO=-2mA Min Max 1.2 0.5 1.3 1.5 0.6 Unit
VOL 1)
V
VOH 2)
Figure 137. Typical VOL at VDD=5V (standard)
Vol [V] at Vdd=5V 2.5 Ta=-40C 2 1.5 1 0.5 0 0 2 4 Iio [mA] 6 8 10 Ta=25C Ta=125C Ta=85C
Figure 139. Typical VDD-VOH at VDD=5V
Vdd-Voh [V] at Vdd=5V 6 5 4 3 2 1 -8 -6 -4 Iio [mA] -2 0 Ta=-40C Ta=25C Ta=85C Ta=125C
Figure 138. Typical VOL at VDD=5V (high-sink)
Vol [V] at Vdd=5V 2 Ta=-40C 1.5 Ta=25C 1 0.5 0 0 5 10 15 Iio [mA] 20 25 30 Ta=125C Ta=85C
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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11.9 CONTROL PIN CHARACTERISTICS 11.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys VOL IIO RON th(RSTL)in tg(RSTL)in Parameter Input low level voltage
1)
Conditions
Min 0.7xVDD
Typ
Max 0.3xVDD
Unit V V
Input high level voltage 1) Schmitt trigger voltage hysteresis 2) Output low level voltage 3) Driving current on RESET pin Weak pull-up equivalent resistor 1) External reset pulse hold time 4) Filtered glitch duration 5) VIN=VSS, VDD=5V Internal reset sources VDD=5V IIO=+5mA IIO=+2mA
1 0.5 0.2 2 20 2.5 450 40 30 80 1.2 0.5
V mA k s s ns
tw(RSTL)out Generated reset pulse duration
Notes: 1. Data based on characterization results, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 5. The reset network protects the device against parasitic resets.
Figure 140. Typical Application with RESET pin 1)2)3)4)5)
Recommended if LVD is disabled
VDD VDD
VDD
ST7FMC
USER EXTERNAL RESET CIRCUIT 8)
0.01F
4.7k
RON
Filter
INTERNAL RESET
0.01F
PULSE GENERATOR
WATCHDOG LVD RESET
Required if LVD is disabled
Notes: 1. The reset network protects the device against parasitic resets. 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 11.9.1 . Otherwise the reset will not be taken into account internally. 4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value specified for IINJ(RESET) in section 11.2.2 on page 244.
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CONTROL PIN CHARACTERISTICS (Cont'd) 11.9.2 ICCSEL/VPP Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH IL Parameter Input low level voltage Input leakage current
1)
Conditions ICC mode entry VIN=VSS
Min VSS VDD-0.1
Max 0.2 12.6 1
Unit
V
Input high level voltage 1) 2)
A
Figure 141. Two typical Applications with VPP Pin 3)
ICCSEL/VPP
PROGRAMMING TOOL 10k
VPP
ST7MC
ST7MC
Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 2. VPP is also used to program the flash , refer to the Flash caracteristics. 3. When the ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.
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11.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 11.10.1 8-Bit PWM-ART Auto-Reload Timer
Symbol Parameter Conditions Min 1 fCPU=8MHz 125 0 0 fCPU/2 fCPU/2 8 VDD=5V, Res=8-bits 20 Typ Max Unit tCPU ns MHz bit mV
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).
tres(PWM) PWM resolution time fEXT fPWM ResPWM VOS ART external clock frequency PWM repetition rate PWM resolution PWM/DAC output step voltage
11.10.2 16-Bit Timer
Symbol Parameter Conditions Min 1 2 fCPU=8MHz 250 0 0 fCPU/4 fCPU/4 16 Typ Max Unit tCPU tCPU ns MHz MHz bit
tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM ResPWM Timer external clock frequency PWM repetition rate PWM resolution
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11.11 COMMUNICATION INTERFACE CHARACTERISTICS 11.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter Master SPI clock frequency fCPU=8MHz Slave fCPU=8MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 0 0.25 0.25 tCPU
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Conditions Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit
MHz
see I/O port pin description 120 120 100 90 100 100 100 100 0 120 240 120
ns
Figure 142. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 143. SPI Slave Timing Diagram with CPHA=11)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 144. SPI Master Timing Diagram
SS INPUT
1)
tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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11.12 MOTOR CONTROL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 11.12.1 Internal Reference Voltage
Symbol Parameter Voltage threshold (VR [2:0] = 000) Voltage threshold (VR [2:0] = 001) Voltage threshold (VR [2:0] = 010) VREF Voltage threshold (VR [2:0] = 011) Voltage threshold (VR [2:0] = 100) Voltage threshold (VR [2:0] = 101) Voltage threshold (VR [2:0] = 110) Conditions VR [2:0] = 000 Example: VDD -VSSA = 5V VR [2:0]= 001 Example: VDD -VSSA = 5V VR [2:0] = 010 Example: VDD -VSSA = 5V VR [2:0]= 011 Example: VDD -VSSA = 5V VR [2:0] = 100 Example: VDD -VSSA = 5V VR [2:0]= 101 Example: VDD -VSSA = 5V VR [2:0] = 110 Example: VDD -VSSA = 5V Min Typ 1) VDD*0.04 0.2 VDD*0.12 0.6 VDD*0.2 1.0 VDD*0.3 1.5 VDD*0.4 2.0 VDD*0.5 2.5 VDD*0.7 3.5 2.5 10 % V Max Unit
VREF/
VREF
Tolerance on VREF
Note : 1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested.
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MOTOR CONTROL CHARACTERISTICS (Cont'd) 11.12.2 Input Stage (comparator + sampling)
Symbol VIN Voffset Ioffset tpropag tstartup Parameter Comparator input voltage range Comparator offset error Input offset current Comparator propagation delay Startup filter duration2) Time waited before sampling when comparator is turned ON, i.e. CKE=1 or DAC=1 (with fPERIPH = 4MHz) Time needed to generate a capture in tachogenerator mode as soon as the MCI input toggles Time needed to capture MTIM in MZREG (BEMF) when sampling during PWM signal OFF time as soon as MCO becomes ON Time needed to set/reset the HST bit when sampling during PWM signal OFF time as soon as MCO becomes ON (BEMF) Time needed to generate Z event (MTIM captured in MZREG) as soon as the comparator toggles (when sampling at fSCF) tsampling Digital sampling delay 3) Time needed to generate D event (MTIM captured in MDREG) as soon as the comparator toggles Time needed to set/reset the HST bit when sampling during PWM signal ON time after a delay (DS>0) as soon as MCO becomes ON Time needed to generate Z event (MTIM in MZREG) when sampling during PWM signal ON time after a delay (DS>0) as soon as MCO becomes ON Time needed to generate Z event (MTIM captured in MZREG) when sampling during PWM signal ON time at fSCF after a delay (DS>0) Conditions Min VSSA - 0.1 5 0 35 Typ Max VDD + 0.1 40 1) 1 100 Unit V mV A ns s
3
4 / fmtc
3 / fmtc (see Figure 145)
1 / fmtc (see Figure 145)
1 / fSCF + 3 / fmtc (see Figure 146)
1 / fSCF + 3 / fmtc (see Figure 146) Delay programmed in DS bits (MCONF) +1 / fmtc (see Figure 147) Delay programmed in DS bits (MCONF) + 3 / fmtc (see Figure 147) Delay programmed in DS bits (MCONF) + 1 / fSCF + 3 / fmtc (see Figure 147)
Note : 1. The comparator accuracy is dependent of the environment. The offset value is given for a comparison done with all digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care must be taken to avoid switching on I/Os close to the inputs when the comparator is in use. This phenomenon is even more critical when a big external serial resistor is added on the inputs. 2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during startup. 3. This delay represents the number of clock cycles needed to generate an event as soon as the comparator output or MCO outputs change. Example : In tachogenerator mode, this means that capture is performed on the 4th clock cycle after comparator commutation., i.e. there is a variation of (1/fmtc) or (1 / fSCF) depending on the case.
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MOTOR CONTROL CHARACTERISTICS (Cont'd) Figure 145. Example 1: Waveforms for Zero-crossing Detection with Sampling at the end of PWM off-time
Sampling time fmtc MCOx Comparator Output Sample HST (MCRC) MTIM A5 A7
A6
MZREG
XX
A5
Figure 146. Example 2: Waveforms for Zero-crossing Detection with Sampling at fSCF
Sampling time fmtc fSCF Comparator Output
Sample HST (MCRC) MTIM A5 A6 A7
MZREG
XX
A6
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MOTOR CONTROL CHARACTERISTICS (Cont'd) Figure 147. Example 3: Waveforms for Zero-crossing Detection with Sampling after a Delay during PWM On-time
Sampling time fmtc MCOx Comparator output sample HST (MCRC) MTIM A5 A7 Delay from DS bits
A6
MZREG
XX
A6
Figure 148. Example 4: Waveforms for zero-crossing detection with sampling after a delay at fSCF
Sampling time fmtc fSCF MCOx comparator output Delay from DS bits sample
HST (MCRC) MTIM A5 A6 A7
MZREG
XX
A7
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MOTOR CONTROL CHARACTERISTICS (Cont'd) 11.12.3 Input Stage (Current Feedback Comparator + Sampling)
Symbol VIN Voffset Ioffset tpropag Parameter Comparator input voltage range Comparator offset error Input offset current Comparator propagation delay 1)
2)
Conditions
Min VSSA - 0.1
Typ 5 0 35
Max VDD + 0.1 40 1 100
1)
Unit V mV A ns
tstartup
Startup filter duration
Time waited before sampling when comparator is turned ON, i.e. CKE=1 or DAC=1 (with fPERIPH = 4MHz) Time needed to turn OFF the MCOs when comparator output rises (CFF=0) Time between a comparator toggle (current loop event) and bit CL becoming set (CFF=0) Time needed to turn OFF the MCOs when comparator output rises (CFF=x) Time between a comparator toggle (current loop event) and bit CL becoming set (CFF=x)
3
s
4 / f MTC (see Figure 149)
2 / f MTC (see Figure 149)
tsampling
Digital sampling delay 3)
(1+x) * (4 / fPERIPH) + (3 / fmtc) (see Figure 150) (1+x) * (4 / fPERIPH) + (1 / fmtc) (see Figure 150)
Note : 1. The comparator accuracy is dependent of the environment. The offset value is given for a comparison done with all digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care must be taken to avoid switching on I/Os close to the inputs when the comparator is in use. This phenomenon is even more critical when a big external serial resistor is added on the inputs. 2. This filter is implemented to wait for comparator stabilization and avoid any wrong information during startup. 3.This delay represents the number of clock cycles needed to generate an event as soon as the comparator ouput changes. Example : When CFF=0 (detection is based on a single detection), MCO outputs are turned OFF at the 4th clock cycle after comparator commutation, i.e. there is a variation of (1/fmtc) or (4 / fPERIPH) depending on the case.
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MOTOR CONTROL CHARACTERISTICS (Cont'd) Figure 149. Example 1 : Waveforms For Overcurrent Detection with Current Feedback Filter OFF
Sampling time fmtc Comparator Output Sample CL (MCRC) MCOx
Figure 150. Example 2 : waveforms for overcurrent detection with current feedback filter ON (CFF=001 => 2 consecutive samples are needed to validate the overcurrent event)
Sampling time fmtc fPERIPH/4 Comparator Output Sample
CL (MCRC) MCOx
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11.13 OPERATIONAL AMPLIFIER CHARACTERISTICS Subject to general operating conditions for fOSC, and TA unless otherwise specified. (TA = -40..+125oC, VDD-VSSA = 4.5..5.5V unless otherwise specified
Symbol RL CL VCMIR Vio Parameter Resistive Load (max 500uA @ 5V) Capacitive Load at VOUT pin Common Mode Input Range Input Offset Voltage ( + or - )
3)
Conditions
Min 10
Typ
Max 150
Unit k pF V mV V/oC mV/V mV/V dB dB V/mV
VSSA After calibration, VIC =1V with respect to temperature with respect to common mode input with respect to supply HIGHGAIN=0 @ 100kHz @ 100kHz RL=10k RL=10k RL=10k HIGHGAIN=0 HIGHGAIN=1 HIGHGAIN=0 (AVCL=1, RL=10k, CL=150pF, Vi=1.75V to 2.75V) 1) HIGHGAIN=0 (AVCL=1, RL=10k, CL=150pF, Vi=1.75V to 2.75V) 1) HIGHGAIN=0 HIGHGAIN=1 0.8 6) 2 2) 7
2)
VDD/2 2.5 10
4)
8.5 5) 1 5) 3.1 5) 74 50
2)
Vio
Input Offset Voltage Drift from the calibrated Voltage, temperature conditions Common Mode Rejection Ratio Supply Voltage Rejection Ratio Voltage Gain High Level Ouptut Saturation Voltage (VDD-VOUT) Low Level Output Saturation Voltage Gain Bandwidth Product
CMR SVR Avd VSAT_OH VSAT_OL GBP
65 12 60 30 4 11 90 2) 90 2) 6 2) 15 2)
(1.5)2)
mV mV MHz
SR
+
Slew Rate while rising
12)
2
V/s
SR
-
Slew Rate while falling
2.52)
7.5
V/s
m Twakeup
Phase Margin Wakeup time for the opamp from off state
73 75 1.6 6)
degrees s
Note : 1. AVCL = closed loop gain 2. Data based on characterization results, not tested in production. 3. after offset compensation has been performed. 4. The amplifier accuracy is dependent of the environment. The offset value is given for a measurement done with all digital I/Os stable. Negative injection current on the I/Os close to the inputs may reduce the accuracy. In particular care must be taken to avoid switching on I/Os close to the inputs when the opamp is in use. This phenomenon is even more critical when a big external serial resistor is added on the inputs. 5. The Data provided from simulations (not tested in production) to guide the user when re-calibration is needed. 6. The Data provided from simulations (not tested in production).
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11.14 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VAREF fADC VAIN Parameter Analog Reference Voltage ADC clock frequency Conversion voltage range 1) Positive input leakage current for analog input Negative input leakage current on analog pins External input impedance External capacitor on analog input Variation freq. of analog input signal Internal sample and hold capacitor Conversion time (Sample+Hold) - Sample capacitor loading time - Hold conversion time Conversion time (Sample+Hold) - Sample capacitor loading time - Hold conversion time RAREF Analog Reference Input Resistor fCPU=8MHz, fADC=4MHz, ADSTS bit in MCCBCR register = 0 fCPU=8MHz, fADC=4MHz, ADSTS bit in MCCBCR register = 1 6 3.5 4 10 6.5 16 10 11 -40CTA85C range Other TA ranges VINIlkg
RAIN CAIN fAIN CADC
tADC
Figure 151. RAIN max. vs f ADC with CAIN=0pF3)
45 40 35
2 MHz 1 MHz
Max. R AIN (Kohm)
30 25 20 15 10 5 0 0 10 30 70
CPARASITIC (pF)
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Figure 152. Recommended CAIN & R AIN values.4)
1000
Cain 10 nF
100
Cain 22 nF Cain 47 nF
Max. R AIN (Kohm)
10
1
0.1 0.01 0.1 1 10
f AIN(KHz)
Figure 153. Typical Application with ADC
VDD VT 0.6V RAIN VAIN CAIN VDD VT 0.6V IL 1A AINx
2k(max)
10-Bit A/D Conversion
CADC 6pF
VAREF
0.1F VSSA RAREF
ST7MC
Notes: 1. When VSSA pins are not available on the pinout, the ADC refer to VSS. 2. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 3. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 4. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN).
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11.14.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate VAREF and VSSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. In some packages, VAREF and VSSA pins are not available (refer to section 2 on page 5). In this case the analog supply and reference pads are internally bonded to the VDD and VSS pins. Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see Section 11.14.2 General PCB Design Guidelines). 11.14.2 General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. - Use separate digital and analog planes. The analog ground plane should be connected to the Figure 154. Power Supply Filtering
1 to 10F
ST7 DIGITAL NOISE FILTERING
digital ground plane via a single point on the PCB. - Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1F and optionally, if needed 10pF capacitors as close as possible to the ST7 power supply pins and a 1 to 10F capacitor close to the power source (see Figure 154). - The analog and digital power supplies should be connected in a star nework. Do not use a resistor, as VAREF is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy. - Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted.
10pF (if needed) 0.1F
ST7MC VSS
VDD
VDD
POWER SUPPLY SOURCE
10pF (if needed) 0.1F
EXTERNAL NOISE FILTERING
VAREF
VSSA
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10-BIT ADC CHARACTERISTICS (Cont'd) ADC Accuracy with VDD=5.0V
Symbol |ET| |EO| |EG| |ED| |EL| Offset error Gain Error Parameter Total unadjusted
1) 1) 1)
Conditions
Typ 4 2.5
Max 4 2) 4 2) 4.5
2)
Unit
error 1) VAREF=3.0V to 5.0V, fCPU=8MHz, fADC=4MHz, RAIN<10k
2 2 2
LSB
Differential linearity error Integral linearity error 1)
4.52)
Notes: 1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input. The effect of negative injection current on analog pins is specified in Section 11.14. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 11.8 does not affect the ADC accuracy. 2. Data based on characterization results, monitored in production.
Figure 155. ADC Accuracy Characteristics
Digital Result ADCDR 1023 1022 1021 1LSB IDEA L V -V DDA SSA = ----------------------------------------
EG
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
1024
(2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Vin (LSBIDEAL) 5 6 7 1021 1022 1023 1024
VAREF
Notes: 1. ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 4 LSB for each 10K increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 2. Data based on characterization results with TA=25C. 3. Data based on characterization results over the whole temperature range, monitored in production.
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ST7MC1/ST7MC2
12 PACKAGE CHARACTERISTICS
12.1 PACKAGE MECHANICAL DATA Figure 156. 80-Pin 14x14 Thin Quad Flat Package
Dim.
D D1 A1 A A2
mm Min 0.05 1.35 0.22 0.09 16.00 14.00 16.00 14.00 0.65 0 0.45 3.5 0.60 1.00 80 7 0 1.40 0.32 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
A A1 A2 b C D
1.45 0.053 0.055 0.057 0.38 0.009 0.013 0.015 0.20 0.004 0.630 0.551 0.630 0.551 0.026 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
e E1 E
D1 E E1 e
L1 L h c
L L1 N
Number of Pins
Figure 157. 64-Pin 14x14 Thin Quad Flat Package
D D1 A1
A A2
Dim. A A1 A2
mm Min 0.05 1.35 0.30 0.09 16.00 14.00 16.00 14.00 0.80 0 0.45 3.5 0.60 1.00 64 7 0 1.40 0.37 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
1.45 0.053 0.055 0.057 0.45 0.012 0.015 0.018 0.20 0.004 0.630 0.551 0.630 0.551 0.031 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
b
b c D
e E1 E
D1 E E1 e L
L L1 c h
L1 N
Number of Pins
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ST7MC1/ST7MC2
PACKAGE CHARACTERISTICS (Cont'd) Figure 158. 44-Pin Thin Quad Flat Package
mm Min 0.05 1.35 0.30 0.09 12.00 10.00 12.00 10.00 0.80 0 0.45 3.5 0.60 1.00 44 7 0 1.40 0.37 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006
D D1 A1 b
A A2
Dim. A A1 A2 b C D
1.45 0.053 0.055 0.057 0.45 0.012 0.015 0.018 0.20 0.004 0.000 0.008 0.472 0.394 0.472 0.394 0.031 3.5 0.039 7 0.75 0.018 0.024 0.030
E1 E
e
D1 E E1 e L L1
L1 L h
c
Number of Pins N
Figure 159. 32-Pin Thin Quad Flat Package
Dim.
D D1 A A2 A1
mm Min 0.05 1.35 0.30 0.09 9.00 7.00 9.00 7.00 0.80 0 0.45 3.5 0.60 1.00 32 7 0 1.40 0.37 Typ Max 1.60 0.15 0.002 Min
inches Typ Max 0.063 0.006
A A1 A2 b C D D1 E E1 e L
h
1.45 0.053 0.055 0.057 0.45 0.012 0.015 0.018 0.20 0.004 0.354 0.276 0.354 0.276 0.031 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
e E1 E
b
L1 L
c
L1 N
Number of Pins
5PACKAGE CHARACTERISTICS (Cont'd)
6
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ST7MC1/ST7MC2
PACKAGE CHARACTERISTICS (Cont'd) Figure 160. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width
mm Min 3.56 0.51 3.05 0.36 0.76 0.20 27.43 7.62 8.89 1.78 10.16 12.70 1.40 2.54 3.05 Number of Pins N 32 3.56 0.46 1.02 0.25 Typ 3.76 Max Min 0.020 4.57 0.120 0.140 0.180 0.58 0.014 0.018 0.023 1.40 0.030 0.040 0.055 0.36 0.008 0.010 0.014 28.45 1.080 1.100 1.120 9.40 0.300 0.350 0.370 0.070 0.400 0.500 0.055 inches Typ Max 5.08 0.140 0.148 0.200
Dim.
E eC
A
A2 A
A1 A2 b
E1 C eA eB
A1
L
b1 C D E E1 e eA eB eC L
b2 D
b
e
9.91 10.41 11.05 0.390 0.410 0.435
3.81 0.100 0.120 0.150
Figure 161. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width
Dim.
E
mm Min 0.38 3.18 0.41 0.89 0.20 50.29 15.01 12.32 1.78 15.24 17.78 2.92 5.08 0.115 14.73 0.485 0.38 0.008 53.21 1.980 Typ Max 6.35 0.015 4.95 0.125 Min
inches Typ Max 0.250 0.195 0.016 0.035 0.015 2.095 0.591 0.580 0.070 0.600 0.700 0.200
A A1 A2
A2 A1
A C
E1 eA
b b2 C
0.015 GAGE PLANE
b2 D
b
e
eB E
D E E1 e eA
eB
eB L N
Number of Pins 56
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ST7MC1/ST7MC2
PACKAGE CHARACTERISTICS (Cont'd) 12.2 THERMAL CHARACTERISTICS
Symbol Ratings Package thermal resistance (junction to ambient) TQFP80 14x14 TQFP64 14x14 TQFP44 10x10 TQFP32 7x7 SDIP32 400mil SDIP56 600mil Power dissipation 1) Maximum junction temperature 2) Value 55 55 68 80 63 45 500 150 Unit
RthJA
C/W
PD TJmax
mW C
Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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ST7MC1/ST7MC2
12.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines. Figure 162. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
250 200 150 Temp. [C] 100 50 0 20 40 60 80 100 120 140 160 PREHEATING PHASE Time [sec] 80C 5 sec SOLDERING PHASE COOLING PHASE (ROOM TEMPERATURE)
Figure 163. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250 200 150 Temp. [C] 100 50 0 100 200 300 400
ramp up 2C/sec for 50sec ramp down natural 2C/sec max 90 sec at 125C 150 sec above 183C Tmax=220+/-5C for 25 sec
Time [sec]
Recommended glue for SMD plastic packages dedicated to molding compound with silicone: s Heraeus: PD945, PD955 s Loctite: 3615, 3298
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ST7MC1/ST7MC2
13 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in ROM versions and in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). ST7MC are ROM devices. ST7PMC devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are programmed FLASH devices. 13.1 FLASH OPTION BYTES
STATIC OPTION BYTE 0 7 CKSEL RSTC WDG HALT SW VD 1 1 0 1 DIV2 0 FMP_R 7 PKG 2 1 1 1 0 1 1 1 1 1 1 STATIC OPTION BYTE 1 0 MCO
ST7FMC FLASH devices are shipped to customers with a default content (FFh), while ROM/FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured.
Default value
1
1
1
1
1
1
The option bytes allow the hardware configuration of the microcontroller to be selected. They have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. This means that all the options have "1" as their default value. OPTION BYTE 0 OPT7= WDG HALT Watchdog and HALT mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode OPT6= WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) OPT5 = CKSEL Clock Source Selection. 0: PLL clock selected 1: Oscillator clock selected OPT4:3= VD[1:0] Voltage detection These option bits enable the voltage detection block (LVD, and AVD).
Selected Low Voltage Detector LVD and AVD On LVD On and AVD Off VD1 0 0 VD0 0 1
Selected Low Voltage Detector LVD and AVD Off
VD1 1 1
VD0 0 1
OPT2 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles applied during the RESET phase and when exiting HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: Reset phase with 4096 CPU cycles 1: Reset phase with 256 CPU cycles Note: When the PLL clock is selected (CKSEL=0), the reset clock cycle selection is forced to 4096 CPU cycles. OPT1= DIV2 Divider by 2 1: DIV2 divider disabled 0: DIV2 divider enabled (in order to have 8 MHz required for the PLL) OPT0= FMP_R Flash memory read-out protection This option indicates if the user flash memory is protected against read-out. This protection is based on a read and write protection of the memory in test modes and ICP mode. Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.3.1 on page 20 for more details. 0: Read-out protection enabled 1: Read-out protection disabled
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ST7MC1/ST7MC2
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) OPTION BYTE 1 OPT7:5= PKG[2:0] package selection These option bits are used to select the device package.
Selected Package TQFP32 / SDIP32 TQFP44 SDIP 56 TQFP64 TQFP80 PKG2 0 0 0 0 1 PKG1 0 0 1 1 x PKG0 0 1 0 1 x
OPT1:0 = MCO Motor Control Output Options MCO port under reset.
Motor Control Output HiZ Low High HiZ bit 1 0 0 1 1 bit 0 0 1 0 1
OPT4:2= Reserved
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ST7MC1/ST7MC2
13.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE The FASTROM or ROM contents are to be sent on Refer to Application Note AN1635 for information diskette, or by electronic means, with the hexadecon the counter listing returned by ST after code imal file in .S19 format generated by the develophas been transferred. ment tool. All unused bytes must be set to FFh. The STMicroelectronics Sales Organization will be The selected options are communicated to STMipleased to provide detailed information on concroelectronics using the correctly completed OPtractual points. TION LIST appended. Table 92. Supported part numbers
Part Number ST7FMC1K2T6 ST7FMC1K2TC ST7FMC1K2B6 ST7FMC2S4T6 ST7FMC2S4TC ST7FMC2S5T6 ST7FMC2S5TC ST7FMC2N6B6 ST7FMC2R6T6 ST7FMC2R7T6 ST7FMC2M9T6 ST7MC1K2T6/xxx ST7MC1K2TC/xxx ST7MC1K2B6/xxx ST7MC2S4T6/xxx ST7MC2S4TC/xxx ST7MC2S5T6/xxx ST7MC2S5TC/xxx ST7MC2N6B6/xxx ST7MC2R6T6/xxx ST7MC2R7T6/xxx ST7MC2M9T6/xxx ST7PMC1K2T6/xxx ST7PMC1K2TC/xxx ST7PMC1K2B6/xxx ST7PMC2S4T6/xxx ST7PMC2S4TC/xxx ST7PMC2S5T6/xxx ST7PMC2S5TC/xxx ST7PMC2N6B6/xxx ST7PMC2R6T6/xxx ST7PMC2R7T6/xxx ST7PMC2M9T6/xxx 16K FASTROM 24K FASTROM 32K FASTROM 48K FASTROM 60K ROM 768 1024 1024 1536 1536 8K FASTROM 384 16K ROM 24K ROM 32K ROM 48K ROM 60K ROM 768 1024 1024 1536 1536 8K ROM 384 16K FLASH 24K FLASH 32K FLASH 48K FLASH 60K FLASH 768 1024 1024 1536 1536 8K FLASH 384 Program Memory (Bytes) RAM (Bytes) Temp. Range -40C +85C -40C +125C -40C +85C -40C +85C -40C +125C -40C +85C -40C +125C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +125C -40C +85C -40C +85C -40C +125C -40C +85C -40C +125C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +125C -40C +85C -40C +85C -40C +125C -40C +85C -40C +125C -40C +85C -40C +85C -40C +85C -40C +85C Package TQFP32 TQFP32 SDIP32 TQFP44 TQFP44 TQFP44 TQFP44 SDIP56 TQFP64 TQFP64 TQFP80 TQFP32 TQFP32 SDIP32 TQFP44 TQFP44 TQFP44 TQFP44 SDIP56 TQFP64 TQFP64 TQFP80 TQFP32 TQFP32 SDIP32 TQFP44 TQFP44 TQFP44 TQFP44 SDIP56 TQFP64 TQFP64 TQFP80
Note: /xxx stands for the ROM or FASTROM code assigned by STMicrolectronics.
Contact ST sales office for product availability
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ST7MC1/ST7MC2
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd)
ST7MC MICROCONTROLLER OPTION LIST ................................ ................................ ................................ Contact: ................................ Phone No: ................................ Reference/ROM or FASTROM Code* : . . . . . . . . . . . . *The ROM or FASTROM code name is assigned by STMicroelectronics. ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Customer: Address: Device Type/Memory Size/Package (check only one option): --------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------60K 48K 32K 24K 16K 8K ROM --------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------TQFP32: | [ ] ST7MC1K2 | | | | | SDIP32: [ ] ST7MC1K2 TQFP44: | | [ ] ST7MC2S4 | [ ] ST7MC2S5 | | | SDIP56: | | | | [ ] ST7MC2N6 | | TQFP64: | | | | [ ] ST7MC2R6 | [ ] ST7MC2R7 | TQFP80 | | | | | | [ ] ST7MC2M9 --------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------8K 16K 24K 32K 48K 60K FASTROM | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | ---------------------------------TQFP32: | [ ] ST7PMC1K2| | | | | SDIP32: [ ] ST7PMC1K2 TQFP44: | | [ ] ST7PMC2S4| [ ] ST7PMC2S5 | | | SDIP56: | | | | [ ] ST7PMC2N6 | | TQFP64: | | | | [ ] ST7PMC2R6 | [ ] ST7PMC2R7| TQFP80 | | | | | | [ ] ST7PMC2M9 Conditioning (check only one option): [ ] Tape & Reel [ ] Tray (TQFP package only) [ ] Tube (SDIP package only) [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)
Special Marking:
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Temperature range:
[ ] - 40C to + 85C [ ] Disabled [ ] Oscillator clock
[ ] - 40C to + 125C [ ] Enabled [ ] PLL clock [ ] Hardware Activation [ ] No reset [ ] Enabled [ ] Enabled [ ] Enabled [ ] 4096 Cycles
DIV2 CKSEL Watchdog Selection: Halt when Watchdog on: Readout Protection:
[ ] Software Activation [ ] Reset [ ] Disabled
LVD Reset [ ] Disabled AVD Interrupt (if LVD enabled) [ ] Disabled Reset Delay [ ] 256 Cycles
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes ................................................................. Date .................................................................
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ST7MC1/ST7MC2
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) 13.3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: http//www.st.com Tools from these manufacturers include C compliers, emulators and gang programmers. Three types of development tool are offered by ST, all of them connect to a PC via a parallel (LPT) port or a USB port: see Table 93 and Table 94 for more details.
Table 93. STMicroelectronics Tool Features
In-Circuit Emulation ST7 EMU3 Emulator Yes, powerful emulation features including trace/ logic analyzer Programming Capability1) Yes with ICC add-on Software Included ST7 CD ROM with: - ST7 Assembly toolchain - STVD7 powerful Source Level Debugger for WinXP, Win 9x, Win 2000, ME and NT4.0 - C compiler demo versions Windows Programming Tools for WinXP, Win 9x , Win 2000, ME and NT4.0
ST7 Programming Board No
Yes (All packages)
Table 94. Dedicated STMicroelectronics Development Tools
Supported Products ST7MC1, ST7MC2 ST7 EMU3 Emulator ST7MDT50-EMU3
Note: 1. Flash Programming interface for FLASH devices.
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ST7MC1/ST7MC2
ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd) 13.3.1 PACKAGE/SOCKET FOOTPRINT PROPOSAL Table 95. Suggested List of Socket Types
Package / Probe TQFP64 14x14 TQFP80 14x14 TQFP32 7x7 TQFP44 10x10 SDIP32 SDIP56 CAB YAMAICHI IRONWOOD YAMAICHI Standard Standard Socket Reference 3303262 IC149-080-*51-*5 SF-QFE32SA-L-01 IC149-044-*52-*5 CAB YAMAICHI IRONWOOD YAMAICHI Standard Standard Emulator Adapter 3303351 ICP-080-7 SK-UGA06/32A-01 ICP-044-5
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ST7MC1/ST7MC2
13.4 ST7 APPLICATION NOTES
IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 IC COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF IC BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 EMULATED 16 BIT SLAVE SPI AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS AN1753 SOFTWARE UART USING 12-BIT ART GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE
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ST7MC1/ST7MC2
IDENTIFICATION DESCRIPTION AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141 AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264 PRODUCT OPTIMIZATION AN 982 USING ST7 WITH CERAMIC RENATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLAAN1530 TOR AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE PROGRAMMING AND TOOLS AN 978 ST7 VISUAL DEBUG SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
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ST7MC1/ST7MC2
IDENTIFICATION DESCRIPTION AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK) AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT SYSTEM OPTIMIZATION AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09
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ST7MC1/ST7MC2
14 SUMMARY OF CHANGES
Revision Main Changes Added ICCSEL to VPP pin (section 2 on page 5) Changed Port Configuration column in Table 1 on page 11 Changed SCIBRR reset value (00h) in Table 2, "Hardware Register Map," on page 16 Added one sentence in "Main Features" section in page 23 Removed references to DIV2 bit in the SICSR register (page 31) Added DIV128 in Figure 17 on page 32 Removed cautions on TRAP and MCES interrupts on page 36 Changed PWM ART row in Table 8, "Interrupt Mapping," on page 40 Changed Section 8.5.1 and Table 12, "Port Configuration," on page 54 Added caution to "External Clock and Event Detector Mode" section. Changed Section 9.6 MOTOR CONTROLLER (MTC) Changed Table 86, "ADC Register Map and Reset Values," on page 236 Changed note 2 in Section 11.2 ABSOLUTE MAXIMUM RATINGS on page 244 Changed section 11.3.1 on page 246 Changed section 11.5.4 on page 254 Changed section 11.9.2 on page 264 Added section 11.12 on page 268 Added section 11.13 on page 274 Changed section 13 on page 284 (Introduction) Changed OPTION BYTE 1 in section 13.1 on page 284 Added reference to AN1635 in section 13.2 on page 286 Added SDIP32 Package option: Symbol & Device Summary updated on Page 1 Package Pinout diagram added Figure 4. "32-Pin SDIP Package Pinouts" page 7 Updated Table 1. "ST7MC Device Pin Description" page 11 Changed 9.6.8.5 "Current feedback amplifier" page 184 to include SDIP32 Changed 12.2 "THERMAL CHARACTERISTICS" page 282 to include SDIP32 Added SDIP32 to Table 92. "Supported part numbers" page 286 Added SDIP32 to Table 95. "Suggested List of Socket Types" page 289 Added Figure 160. "32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width" page 281 Altered Figure 4. "32-Pin SDIP Package Pinouts" page 7 such that ei0 does not include PD0 Modifications made to text on Page 1 under `Motor Control Peripheral' subheading Alteration of 11.3.1 "General Operating Conditions" page 246 data plus addition of corresponding Figure 128. "fCPU Max Versus VDD" page 246 Added consumption graphs and values or RUN, WAIT, SLOW, SLOW-WAIT modes Added values into 11.3.3 "Auxiliary Voltage Detector (AVD) Thresholds" page 247 Altered values of 11.4.4 "Supply and Clock Managers" page 250 Added values into 11.4.5 "On-Chip Peripherals" page 251 Added values into 11.5.3 "Crystal and Ceramic Resonator Oscillators" page 253 Added values into 11.6.2 "FLASH Memory" page 256 Updated ESD (machine model) value in section 11.7.3.1 on page 259 Added values into 11.7.3.2 "Static and Dynamic Latch-Up" page 259 Altered values and table in 11.13OPERATIONAL AMPLIFIER CHARACTERISTICS Put note referring to PC4 in all pinouts and in Table 1 on page 11 Moved section "10-bit A/D Converter (ADC)" from 9.6.14 to Section 9.8 Figure 76 on page 144, MCRB changed to MCRC, Freq(T=1s) replaced by fSCF Table in section 11.5.3 on page 253 updated with reference to capacitance table Updated Emulator Tool features, Table 93 Device alteration: ST7MC2 24K has 1024bytes RAM instead of 768bytes: updated Device Summary table page 1, Table 92. on page 286 Negative injection note addition added to Section 11.12.2, Section 11.12.3 and Section 11.13 "Even / Odd" reworded as "High / Low" from Section 9.6.2 to Section 9.6.13 inclusive. SR=1 column added to Table 27 on page 146 and Table 71 on page 212 Thermal Characteristics Section 12.2 values updated Date
2.0
Nov 03
2.1
Apr 04
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ST7MC1/ST7MC2
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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